1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/socione 4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Socionext UniPhier PCIe PHY 7 title: Socionext UniPhier PCIe PHY
8 8
9 description: | 9 description: |
10 This describes the devicetree bindings for P 10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext Uni 11 PCIe controller implemented on Socionext UniPhier SoCs.
12 12
13 maintainers: 13 maintainers:
14 - Kunihiko Hayashi <hayashi.kunihiko@socionex 14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - socionext,uniphier-pro5-pcie-phy 19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy 20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy 21 - socionext,uniphier-pxs3-pcie-phy
22 - socionext,uniphier-nx1-pcie-phy <<
23 22
24 reg: 23 reg:
25 maxItems: 1 24 maxItems: 1
26 25
27 "#phy-cells": 26 "#phy-cells":
28 const: 0 27 const: 0
29 28
30 clocks: 29 clocks:
31 minItems: 1 30 minItems: 1
32 maxItems: 2 31 maxItems: 2
33 32
34 clock-names: 33 clock-names:
35 minItems: 1 !! 34 oneOf:
36 maxItems: 2 !! 35 - items: # for Pro5
>> 36 - const: gio
>> 37 - const: link
>> 38 - const: link # for others
37 39
38 resets: 40 resets:
39 minItems: 1 41 minItems: 1
40 maxItems: 2 42 maxItems: 2
41 43
42 reset-names: 44 reset-names:
43 minItems: 1 !! 45 oneOf:
44 maxItems: 2 !! 46 - items: # for Pro5
>> 47 - const: gio
>> 48 - const: link
>> 49 - const: link # for others
45 50
46 socionext,syscon: 51 socionext,syscon:
47 $ref: /schemas/types.yaml#/definitions/pha 52 $ref: /schemas/types.yaml#/definitions/phandle
48 description: A phandle to system control t 53 description: A phandle to system control to set configurations for phy
49 <<
50 allOf: <<
51 - if: <<
52 properties: <<
53 compatible: <<
54 contains: <<
55 const: socionext,uniphier-pro5-pci <<
56 then: <<
57 properties: <<
58 clocks: <<
59 minItems: 2 <<
60 maxItems: 2 <<
61 clock-names: <<
62 items: <<
63 - const: gio <<
64 - const: link <<
65 resets: <<
66 minItems: 2 <<
67 maxItems: 2 <<
68 reset-names: <<
69 items: <<
70 - const: gio <<
71 - const: link <<
72 else: <<
73 properties: <<
74 clocks: <<
75 maxItems: 1 <<
76 clock-names: <<
77 const: link <<
78 resets: <<
79 maxItems: 1 <<
80 reset-names: <<
81 const: link <<
82 54
83 required: 55 required:
84 - compatible 56 - compatible
85 - reg 57 - reg
86 - "#phy-cells" 58 - "#phy-cells"
87 - clocks 59 - clocks
88 - clock-names 60 - clock-names
89 - resets 61 - resets
90 - reset-names 62 - reset-names
91 63
92 additionalProperties: false 64 additionalProperties: false
93 65
94 examples: 66 examples:
95 - | 67 - |
96 pcie_phy: phy@66038000 { 68 pcie_phy: phy@66038000 {
97 compatible = "socionext,uniphier-ld20- 69 compatible = "socionext,uniphier-ld20-pcie-phy";
98 reg = <0x66038000 0x4000>; 70 reg = <0x66038000 0x4000>;
99 #phy-cells = <0>; 71 #phy-cells = <0>;
100 clock-names = "link"; 72 clock-names = "link";
101 clocks = <&sys_clk 24>; 73 clocks = <&sys_clk 24>;
102 reset-names = "link"; 74 reset-names = "link";
103 resets = <&sys_rst 24>; 75 resets = <&sys_rst 24>;
104 socionext,syscon = <&soc_glue>; 76 socionext,syscon = <&soc_glue>;
105 }; 77 };
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