1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/socione 4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Socionext UniPhier PCIe PHY 7 title: Socionext UniPhier PCIe PHY
8 8
9 description: | 9 description: |
10 This describes the devicetree bindings for P 10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext Uni 11 PCIe controller implemented on Socionext UniPhier SoCs.
12 12
13 maintainers: 13 maintainers:
14 - Kunihiko Hayashi <hayashi.kunihiko@socionex 14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - socionext,uniphier-pro5-pcie-phy 19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy 20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy 21 - socionext,uniphier-pxs3-pcie-phy
22 - socionext,uniphier-nx1-pcie-phy 22 - socionext,uniphier-nx1-pcie-phy
23 23
24 reg: 24 reg:
25 maxItems: 1 25 maxItems: 1
26 26
27 "#phy-cells": 27 "#phy-cells":
28 const: 0 28 const: 0
29 29
30 clocks: 30 clocks:
31 minItems: 1 31 minItems: 1
32 maxItems: 2 32 maxItems: 2
33 33
34 clock-names: !! 34 clock-names: true
35 minItems: 1 <<
36 maxItems: 2 <<
37 35
38 resets: 36 resets:
39 minItems: 1 37 minItems: 1
40 maxItems: 2 38 maxItems: 2
41 39
42 reset-names: !! 40 reset-names: true
43 minItems: 1 <<
44 maxItems: 2 <<
45 41
46 socionext,syscon: 42 socionext,syscon:
47 $ref: /schemas/types.yaml#/definitions/pha 43 $ref: /schemas/types.yaml#/definitions/phandle
48 description: A phandle to system control t 44 description: A phandle to system control to set configurations for phy
49 45
50 allOf: 46 allOf:
51 - if: 47 - if:
52 properties: 48 properties:
53 compatible: 49 compatible:
54 contains: 50 contains:
55 const: socionext,uniphier-pro5-pci 51 const: socionext,uniphier-pro5-pcie-phy
56 then: 52 then:
57 properties: 53 properties:
58 clocks: 54 clocks:
59 minItems: 2 55 minItems: 2
60 maxItems: 2 56 maxItems: 2
61 clock-names: 57 clock-names:
62 items: 58 items:
63 - const: gio 59 - const: gio
64 - const: link 60 - const: link
65 resets: 61 resets:
66 minItems: 2 62 minItems: 2
67 maxItems: 2 63 maxItems: 2
68 reset-names: 64 reset-names:
69 items: 65 items:
70 - const: gio 66 - const: gio
71 - const: link 67 - const: link
72 else: 68 else:
73 properties: 69 properties:
74 clocks: 70 clocks:
75 maxItems: 1 71 maxItems: 1
76 clock-names: 72 clock-names:
77 const: link 73 const: link
78 resets: 74 resets:
79 maxItems: 1 75 maxItems: 1
80 reset-names: 76 reset-names:
81 const: link 77 const: link
82 78
83 required: 79 required:
84 - compatible 80 - compatible
85 - reg 81 - reg
86 - "#phy-cells" 82 - "#phy-cells"
87 - clocks 83 - clocks
88 - clock-names 84 - clock-names
89 - resets 85 - resets
90 - reset-names 86 - reset-names
91 87
92 additionalProperties: false 88 additionalProperties: false
93 89
94 examples: 90 examples:
95 - | 91 - |
96 pcie_phy: phy@66038000 { 92 pcie_phy: phy@66038000 {
97 compatible = "socionext,uniphier-ld20- 93 compatible = "socionext,uniphier-ld20-pcie-phy";
98 reg = <0x66038000 0x4000>; 94 reg = <0x66038000 0x4000>;
99 #phy-cells = <0>; 95 #phy-cells = <0>;
100 clock-names = "link"; 96 clock-names = "link";
101 clocks = <&sys_clk 24>; 97 clocks = <&sys_clk 24>;
102 reset-names = "link"; 98 reset-names = "link";
103 resets = <&sys_rst 24>; 99 resets = <&sys_rst 24>;
104 socionext,syscon = <&soc_glue>; 100 socionext,syscon = <&soc_glue>;
105 }; 101 };
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