1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy- 4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: TI AM654 SERDES 7 title: TI AM654 SERDES
8 8
9 description: 9 description:
10 This binding describes the TI AM654 SERDES. 10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
11 to be used with either PCIe or USB or SGMII. 11 to be used with either PCIe or USB or SGMII.
12 12
13 maintainers: 13 maintainers:
14 - Kishon Vijay Abraham I <kishon@ti.com> 14 - Kishon Vijay Abraham I <kishon@ti.com>
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - ti,phy-am654-serdes 19 - ti,phy-am654-serdes
20 20
21 reg: 21 reg:
22 maxItems: 1 22 maxItems: 1
23 23
24 reg-names: 24 reg-names:
25 items: 25 items:
26 - const: serdes 26 - const: serdes
27 27
28 power-domains: 28 power-domains:
29 maxItems: 1 29 maxItems: 1
30 30
31 clocks: 31 clocks:
32 maxItems: 3 32 maxItems: 3
33 description: 33 description:
34 Three input clocks referring to left inp 34 Three input clocks referring to left input reference clock, refclk and right input reference
35 clock. 35 clock.
36 36
>> 37 assigned-clocks:
>> 38 $ref: "/schemas/types.yaml#/definitions/phandle-array"
>> 39 assigned-clock-parents:
>> 40 $ref: "/schemas/types.yaml#/definitions/phandle-array"
>> 41
37 '#phy-cells': 42 '#phy-cells':
38 const: 2 43 const: 2
39 description: 44 description:
40 The 1st cell corresponds to the phy type 45 The 1st cell corresponds to the phy type (should be one of the types specified in
41 include/dt-bindings/phy/phy.h) and the 2 46 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
42 47
43 ti,serdes-clk: 48 ti,serdes-clk:
44 description: Phandle to the SYSCON entry r 49 description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
45 $ref: /schemas/types.yaml#/definitions/pha 50 $ref: /schemas/types.yaml#/definitions/phandle
46 51
47 '#clock-cells': 52 '#clock-cells':
48 const: 1 53 const: 1
49 54
50 mux-controls: 55 mux-controls:
51 maxItems: 1 56 maxItems: 1
52 description: Phandle to the SYSCON entry r 57 description: Phandle to the SYSCON entry required for configuring SERDES lane function.
53 58
54 clock-output-names: 59 clock-output-names:
55 oneOf: 60 oneOf:
56 - description: Clock output names for SE 61 - description: Clock output names for SERDES 0
57 items: 62 items:
58 - const: serdes0_cmu_refclk 63 - const: serdes0_cmu_refclk
59 - const: serdes0_lo_refclk 64 - const: serdes0_lo_refclk
60 - const: serdes0_ro_refclk 65 - const: serdes0_ro_refclk
61 - description: Clock output names for SE 66 - description: Clock output names for SERDES 1
62 items: 67 items:
63 - const: serdes1_cmu_refclk 68 - const: serdes1_cmu_refclk
64 - const: serdes1_lo_refclk 69 - const: serdes1_lo_refclk
65 - const: serdes1_ro_refclk 70 - const: serdes1_ro_refclk
66 71
67 required: 72 required:
68 - compatible 73 - compatible
69 - reg 74 - reg
70 - power-domains 75 - power-domains
71 - clocks 76 - clocks
72 - assigned-clocks 77 - assigned-clocks
73 - assigned-clock-parents 78 - assigned-clock-parents
74 - ti,serdes-clk 79 - ti,serdes-clk
75 - mux-controls 80 - mux-controls
76 - clock-output-names 81 - clock-output-names
77 82
78 additionalProperties: false 83 additionalProperties: false
79 84
80 examples: 85 examples:
81 - | 86 - |
82 #include <dt-bindings/phy/phy-am654-serdes 87 #include <dt-bindings/phy/phy-am654-serdes.h>
83 88
84 serdes0: serdes@900000 { 89 serdes0: serdes@900000 {
85 compatible = "ti,phy-am654-serdes"; 90 compatible = "ti,phy-am654-serdes";
86 reg = <0x900000 0x2000>; 91 reg = <0x900000 0x2000>;
87 reg-names = "serdes"; 92 reg-names = "serdes";
88 #phy-cells = <2>; 93 #phy-cells = <2>;
89 power-domains = <&k3_pds 153>; 94 power-domains = <&k3_pds 153>;
90 clocks = <&k3_clks 153 4>, <&k3_clks 153 95 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>,
91 <&serdes1 AM654_SERDES_LO_REFCL 96 <&serdes1 AM654_SERDES_LO_REFCLK>;
92 clock-output-names = "serdes0_cmu_refclk 97 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
93 assigned-clocks = <&k3_clks 153 4>, <&se 98 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
94 assigned-clock-parents = <&k3_clks 153 8 99 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
95 ti,serdes-clk = <&serdes0_clk>; 100 ti,serdes-clk = <&serdes0_clk>;
96 mux-controls = <&serdes_mux 0>; 101 mux-controls = <&serdes_mux 0>;
97 #clock-cells = <1>; 102 #clock-cells = <1>;
98 }; 103 };
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