1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorpo 2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- !! 5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: CPSW Port's Interface Mode Selection PH !! 8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 description: | 13 description: |
14 TI am335x/am437x/dra7(am5)/dm814x CPSW3G Eth 14 TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
15 two 10/100/1000 Ethernet ports with selectab 15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16 The interface mode is selected by configurin 16 The interface mode is selected by configuring the MII mode selection register(s)
17 (GMII_SEL) in the System Control Module chap 17 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
18 bit fields placement in SCM are different be 18 bit fields placement in SCM are different between SoCs while fields meaning
19 is the same. 19 is the same.
20 20 +--------------+
21 +-------------------------------+ 21 +-------------------------------+ |SCM |
22 | CPSW | 22 | CPSW | | +---------+ |
23 | +---------------------------- 23 | +--------------------------------+gmii_sel | |
24 | | | 24 | | | | +---------+ |
25 | +----v---+ +--------+ | 25 | +----v---+ +--------+ | +--------------+
26 | |Port 1..<--+-->GMII/MII<-------> 26 | |Port 1..<--+-->GMII/MII<------->
27 | | | | | | | 27 | | | | | | |
28 | +--------+ | +--------+ | 28 | +--------+ | +--------+ |
29 | | | 29 | | |
30 | | +--------+ | 30 | | +--------+ |
31 | | | RMII <-------> 31 | | | RMII <------->
32 | +--> | | 32 | +--> | |
33 | | +--------+ | 33 | | +--------+ |
34 | | | 34 | | |
35 | | +--------+ | 35 | | +--------+ |
36 | | | RGMII <-------> 36 | | | RGMII <------->
37 | +--> | | 37 | +--> | |
38 | +--------+ | 38 | +--------+ |
39 +-------------------------------+ 39 +-------------------------------+
40 40
41 CPSW Port's Interface Mode Selection PHY des 41 CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42 CPSW Port and Ethernet PHY which depends on 42 CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
43 | 43 |
44 CPSW Port's Interface Mode Selection PHY dev 44 CPSW Port's Interface Mode Selection PHY device should defined as child device
45 of SCM node (scm_conf) and can be attached t 45 of SCM node (scm_conf) and can be attached to each CPSW port node using standard
46 PHY bindings. 46 PHY bindings.
47 47
48 properties: 48 properties:
49 compatible: 49 compatible:
50 enum: 50 enum:
51 - ti,am3352-phy-gmii-sel 51 - ti,am3352-phy-gmii-sel
52 - ti,dra7xx-phy-gmii-sel 52 - ti,dra7xx-phy-gmii-sel
53 - ti,am43xx-phy-gmii-sel 53 - ti,am43xx-phy-gmii-sel
54 - ti,dm814-phy-gmii-sel 54 - ti,dm814-phy-gmii-sel
55 - ti,am654-phy-gmii-sel 55 - ti,am654-phy-gmii-sel
56 - ti,j7200-cpsw5g-phy-gmii-sel <<
57 - ti,j721e-cpsw9g-phy-gmii-sel <<
58 - ti,j784s4-cpsw9g-phy-gmii-sel <<
59 56
60 reg: 57 reg:
61 maxItems: 1 58 maxItems: 1
62 59
63 '#phy-cells': true 60 '#phy-cells': true
64 61
65 ti,qsgmii-main-ports: <<
66 $ref: /schemas/types.yaml#/definitions/uin <<
67 description: | <<
68 Required only for QSGMII mode. Array to <<
69 main mode. The size of the array corresp <<
70 interfaces and thus, the number of disti <<
71 supported by the device. If the device s <<
72 but only one QSGMII interface is desired <<
73 value corresponding to the QSGMII interf <<
74 minItems: 1 <<
75 maxItems: 2 <<
76 items: <<
77 minimum: 1 <<
78 maximum: 8 <<
79 <<
80 allOf: 62 allOf:
81 - if: 63 - if:
82 properties: 64 properties:
83 compatible: 65 compatible:
84 contains: 66 contains:
85 enum: 67 enum:
86 - ti,dra7xx-phy-gmii-sel 68 - ti,dra7xx-phy-gmii-sel
87 - ti,dm814-phy-gmii-sel 69 - ti,dm814-phy-gmii-sel
88 - ti,am654-phy-gmii-sel 70 - ti,am654-phy-gmii-sel
89 - ti,j7200-cpsw5g-phy-gmii-sel <<
90 - ti,j721e-cpsw9g-phy-gmii-sel <<
91 - ti,j784s4-cpsw9g-phy-gmii-sel <<
92 then: 71 then:
93 properties: 72 properties:
94 '#phy-cells': 73 '#phy-cells':
95 const: 1 74 const: 1
96 description: CPSW port number (start 75 description: CPSW port number (starting from 1)
97 <<
98 - if: <<
99 properties: <<
100 compatible: <<
101 contains: <<
102 enum: <<
103 - ti,j7200-cpsw5g-phy-gmii-sel <<
104 then: <<
105 properties: <<
106 ti,qsgmii-main-ports: <<
107 maxItems: 1 <<
108 items: <<
109 minimum: 1 <<
110 maximum: 4 <<
111 <<
112 - if: <<
113 properties: <<
114 compatible: <<
115 contains: <<
116 enum: <<
117 - ti,j721e-cpsw9g-phy-gmii-sel <<
118 - ti,j784s4-cpsw9g-phy-gmii-sel <<
119 then: <<
120 properties: <<
121 ti,qsgmii-main-ports: <<
122 minItems: 2 <<
123 maxItems: 2 <<
124 items: <<
125 minimum: 1 <<
126 maximum: 8 <<
127 <<
128 - if: <<
129 not: <<
130 properties: <<
131 compatible: <<
132 contains: <<
133 enum: <<
134 - ti,j7200-cpsw5g-phy-gmii-sel <<
135 - ti,j721e-cpsw9g-phy-gmii-sel <<
136 - ti,j784s4-cpsw9g-phy-gmii-se <<
137 then: <<
138 properties: <<
139 ti,qsgmii-main-ports: false <<
140 <<
141 - if: 76 - if:
142 properties: 77 properties:
143 compatible: 78 compatible:
144 contains: 79 contains:
145 enum: 80 enum:
146 - ti,am3352-phy-gmii-sel 81 - ti,am3352-phy-gmii-sel
147 - ti,am43xx-phy-gmii-sel 82 - ti,am43xx-phy-gmii-sel
148 then: 83 then:
149 properties: 84 properties:
150 '#phy-cells': 85 '#phy-cells':
151 const: 2 86 const: 2
152 description: | 87 description: |
153 - CPSW port number (starting from 88 - CPSW port number (starting from 1)
154 - RMII refclk mode 89 - RMII refclk mode
155 90
156 required: 91 required:
157 - compatible 92 - compatible
158 - reg 93 - reg
159 - '#phy-cells' 94 - '#phy-cells'
160 95
161 additionalProperties: false 96 additionalProperties: false
162 97
163 examples: 98 examples:
164 - | 99 - |
165 phy_gmii_sel: phy@650 { !! 100 phy_gmii_sel: phy-gmii-sel@650 {
166 compatible = "ti,am3352-phy-gmii-sel"; 101 compatible = "ti,am3352-phy-gmii-sel";
167 reg = <0x650 0x4>; 102 reg = <0x650 0x4>;
168 #phy-cells = <2>; 103 #phy-cells = <2>;
169 }; 104 };
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