1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorpo 2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- 5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: CPSW Port's Interface Mode Selection PH 8 title: CPSW Port's Interface Mode Selection PHY
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 description: | 13 description: |
14 TI am335x/am437x/dra7(am5)/dm814x CPSW3G Eth 14 TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
15 two 10/100/1000 Ethernet ports with selectab 15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16 The interface mode is selected by configurin 16 The interface mode is selected by configuring the MII mode selection register(s)
17 (GMII_SEL) in the System Control Module chap 17 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
18 bit fields placement in SCM are different be 18 bit fields placement in SCM are different between SoCs while fields meaning
19 is the same. 19 is the same.
20 20 +--------------+
21 +-------------------------------+ 21 +-------------------------------+ |SCM |
22 | CPSW | 22 | CPSW | | +---------+ |
23 | +---------------------------- 23 | +--------------------------------+gmii_sel | |
24 | | | 24 | | | | +---------+ |
25 | +----v---+ +--------+ | 25 | +----v---+ +--------+ | +--------------+
26 | |Port 1..<--+-->GMII/MII<-------> 26 | |Port 1..<--+-->GMII/MII<------->
27 | | | | | | | 27 | | | | | | |
28 | +--------+ | +--------+ | 28 | +--------+ | +--------+ |
29 | | | 29 | | |
30 | | +--------+ | 30 | | +--------+ |
31 | | | RMII <-------> 31 | | | RMII <------->
32 | +--> | | 32 | +--> | |
33 | | +--------+ | 33 | | +--------+ |
34 | | | 34 | | |
35 | | +--------+ | 35 | | +--------+ |
36 | | | RGMII <-------> 36 | | | RGMII <------->
37 | +--> | | 37 | +--> | |
38 | +--------+ | 38 | +--------+ |
39 +-------------------------------+ 39 +-------------------------------+
40 40
41 CPSW Port's Interface Mode Selection PHY des 41 CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42 CPSW Port and Ethernet PHY which depends on 42 CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
43 | 43 |
44 CPSW Port's Interface Mode Selection PHY dev 44 CPSW Port's Interface Mode Selection PHY device should defined as child device
45 of SCM node (scm_conf) and can be attached t 45 of SCM node (scm_conf) and can be attached to each CPSW port node using standard
46 PHY bindings. 46 PHY bindings.
47 47
48 properties: 48 properties:
49 compatible: 49 compatible:
50 enum: 50 enum:
51 - ti,am3352-phy-gmii-sel 51 - ti,am3352-phy-gmii-sel
52 - ti,dra7xx-phy-gmii-sel 52 - ti,dra7xx-phy-gmii-sel
53 - ti,am43xx-phy-gmii-sel 53 - ti,am43xx-phy-gmii-sel
54 - ti,dm814-phy-gmii-sel 54 - ti,dm814-phy-gmii-sel
55 - ti,am654-phy-gmii-sel 55 - ti,am654-phy-gmii-sel
56 - ti,j7200-cpsw5g-phy-gmii-sel 56 - ti,j7200-cpsw5g-phy-gmii-sel
57 - ti,j721e-cpsw9g-phy-gmii-sel 57 - ti,j721e-cpsw9g-phy-gmii-sel
58 - ti,j784s4-cpsw9g-phy-gmii-sel 58 - ti,j784s4-cpsw9g-phy-gmii-sel
59 59
60 reg: 60 reg:
61 maxItems: 1 61 maxItems: 1
62 62
63 '#phy-cells': true 63 '#phy-cells': true
64 64
65 ti,qsgmii-main-ports: 65 ti,qsgmii-main-ports:
66 $ref: /schemas/types.yaml#/definitions/uin 66 $ref: /schemas/types.yaml#/definitions/uint32-array
67 description: | 67 description: |
68 Required only for QSGMII mode. Array to 68 Required only for QSGMII mode. Array to select the port/s for QSGMII
69 main mode. The size of the array corresp 69 main mode. The size of the array corresponds to the number of QSGMII
70 interfaces and thus, the number of disti 70 interfaces and thus, the number of distinct QSGMII main ports,
71 supported by the device. If the device s 71 supported by the device. If the device supports two QSGMII interfaces
72 but only one QSGMII interface is desired 72 but only one QSGMII interface is desired, repeat the QSGMII main port
73 value corresponding to the QSGMII interf 73 value corresponding to the QSGMII interface in the array.
74 minItems: 1 74 minItems: 1
75 maxItems: 2 75 maxItems: 2
76 items: 76 items:
77 minimum: 1 77 minimum: 1
78 maximum: 8 78 maximum: 8
79 79
80 allOf: 80 allOf:
81 - if: 81 - if:
82 properties: 82 properties:
83 compatible: 83 compatible:
84 contains: 84 contains:
85 enum: 85 enum:
86 - ti,dra7xx-phy-gmii-sel 86 - ti,dra7xx-phy-gmii-sel
87 - ti,dm814-phy-gmii-sel 87 - ti,dm814-phy-gmii-sel
88 - ti,am654-phy-gmii-sel 88 - ti,am654-phy-gmii-sel
89 - ti,j7200-cpsw5g-phy-gmii-sel 89 - ti,j7200-cpsw5g-phy-gmii-sel
90 - ti,j721e-cpsw9g-phy-gmii-sel 90 - ti,j721e-cpsw9g-phy-gmii-sel
91 - ti,j784s4-cpsw9g-phy-gmii-sel 91 - ti,j784s4-cpsw9g-phy-gmii-sel
92 then: 92 then:
93 properties: 93 properties:
94 '#phy-cells': 94 '#phy-cells':
95 const: 1 95 const: 1
96 description: CPSW port number (start 96 description: CPSW port number (starting from 1)
97 97
98 - if: 98 - if:
99 properties: 99 properties:
100 compatible: 100 compatible:
101 contains: 101 contains:
102 enum: 102 enum:
103 - ti,j7200-cpsw5g-phy-gmii-sel 103 - ti,j7200-cpsw5g-phy-gmii-sel
104 then: 104 then:
105 properties: 105 properties:
106 ti,qsgmii-main-ports: 106 ti,qsgmii-main-ports:
107 maxItems: 1 107 maxItems: 1
108 items: 108 items:
109 minimum: 1 109 minimum: 1
110 maximum: 4 110 maximum: 4
111 111
112 - if: 112 - if:
113 properties: 113 properties:
114 compatible: 114 compatible:
115 contains: 115 contains:
116 enum: 116 enum:
117 - ti,j721e-cpsw9g-phy-gmii-sel 117 - ti,j721e-cpsw9g-phy-gmii-sel
118 - ti,j784s4-cpsw9g-phy-gmii-sel 118 - ti,j784s4-cpsw9g-phy-gmii-sel
119 then: 119 then:
120 properties: 120 properties:
121 ti,qsgmii-main-ports: 121 ti,qsgmii-main-ports:
122 minItems: 2 122 minItems: 2
123 maxItems: 2 123 maxItems: 2
124 items: 124 items:
125 minimum: 1 125 minimum: 1
126 maximum: 8 126 maximum: 8
127 127
128 - if: 128 - if:
129 not: 129 not:
130 properties: 130 properties:
131 compatible: 131 compatible:
132 contains: 132 contains:
133 enum: 133 enum:
134 - ti,j7200-cpsw5g-phy-gmii-sel 134 - ti,j7200-cpsw5g-phy-gmii-sel
135 - ti,j721e-cpsw9g-phy-gmii-sel 135 - ti,j721e-cpsw9g-phy-gmii-sel
136 - ti,j784s4-cpsw9g-phy-gmii-se 136 - ti,j784s4-cpsw9g-phy-gmii-sel
137 then: 137 then:
138 properties: 138 properties:
139 ti,qsgmii-main-ports: false 139 ti,qsgmii-main-ports: false
140 140
141 - if: 141 - if:
142 properties: 142 properties:
143 compatible: 143 compatible:
144 contains: 144 contains:
145 enum: 145 enum:
146 - ti,am3352-phy-gmii-sel 146 - ti,am3352-phy-gmii-sel
147 - ti,am43xx-phy-gmii-sel 147 - ti,am43xx-phy-gmii-sel
148 then: 148 then:
149 properties: 149 properties:
150 '#phy-cells': 150 '#phy-cells':
151 const: 2 151 const: 2
152 description: | 152 description: |
153 - CPSW port number (starting from 153 - CPSW port number (starting from 1)
154 - RMII refclk mode 154 - RMII refclk mode
155 155
156 required: 156 required:
157 - compatible 157 - compatible
158 - reg 158 - reg
159 - '#phy-cells' 159 - '#phy-cells'
160 160
161 additionalProperties: false 161 additionalProperties: false
162 162
163 examples: 163 examples:
164 - | 164 - |
165 phy_gmii_sel: phy@650 { 165 phy_gmii_sel: phy@650 {
166 compatible = "ti,am3352-phy-gmii-sel"; 166 compatible = "ti,am3352-phy-gmii-sel";
167 reg = <0x650 0x4>; 167 reg = <0x650 0x4>;
168 #phy-cells = <2>; 168 #phy-cells = <2>;
169 }; 169 };
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