1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorpo 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- !! 5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: TI J721E WIZ (SERDES Wrapper) 8 title: TI J721E WIZ (SERDES Wrapper)
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 enum: 15 enum:
16 - ti,j721e-wiz-16g 16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g 17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g <<
19 - ti,am64-wiz-10g <<
20 - ti,j7200-wiz-10g <<
21 - ti,j784s4-wiz-10g <<
22 18
23 power-domains: 19 power-domains:
24 maxItems: 1 20 maxItems: 1
25 21
26 clocks: 22 clocks:
27 minItems: 3 !! 23 maxItems: 3
28 maxItems: 4 <<
29 description: clock-specifier to represent 24 description: clock-specifier to represent input to the WIZ
30 25
31 clock-names: 26 clock-names:
32 minItems: 3 <<
33 items: 27 items:
34 - const: fck 28 - const: fck
35 - const: core_ref_clk 29 - const: core_ref_clk
36 - const: ext_ref_clk 30 - const: ext_ref_clk
37 - const: core_ref1_clk <<
38 31
39 num-lanes: 32 num-lanes:
40 minimum: 1 33 minimum: 1
41 maximum: 4 34 maximum: 4
42 35
43 "#address-cells": 36 "#address-cells":
44 const: 1 37 const: 1
45 38
46 "#size-cells": 39 "#size-cells":
47 const: 1 40 const: 1
48 41
49 "#reset-cells": 42 "#reset-cells":
50 const: 1 43 const: 1
51 44
52 "#clock-cells": <<
53 const: 1 <<
54 <<
55 ranges: true 45 ranges: true
56 46
>> 47 assigned-clocks:
>> 48 minItems: 1
>> 49 maxItems: 2
>> 50
>> 51 assigned-clock-parents:
>> 52 minItems: 1
>> 53 maxItems: 2
>> 54
>> 55 assigned-clock-rates:
>> 56 minItems: 1
>> 57 maxItems: 2
>> 58
57 typec-dir-gpios: 59 typec-dir-gpios:
58 maxItems: 1 60 maxItems: 1
59 description: 61 description:
60 GPIO to signal Type-C cable orientation 62 GPIO to signal Type-C cable orientation for lane swap.
61 If GPIO is active, lane 0 and lane 1 of 63 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
62 achieve the functionality of an external !! 64 achieve the funtionality of an external type-C plug flip mux.
63 65
64 typec-dir-debounce-ms: 66 typec-dir-debounce-ms:
65 minimum: 100 67 minimum: 100
66 maximum: 1000 68 maximum: 1000
67 default: 100 69 default: 100
68 description: 70 description:
69 Number of milliseconds to wait before sa 71 Number of milliseconds to wait before sampling typec-dir-gpio.
70 If not specified, the default debounce o 72 If not specified, the default debounce of 100ms will be used.
71 Type-C spec states minimum CC pin deboun 73 Type-C spec states minimum CC pin debounce of 100 ms and maximum
72 of 200 ms. However, some solutions might 74 of 200 ms. However, some solutions might need more than 200 ms.
73 75
74 refclk-dig: <<
75 type: object <<
76 additionalProperties: false <<
77 description: | <<
78 WIZ node should have subnode for refclk_ <<
79 clock source for the reference clock use <<
80 logic. <<
81 deprecated: true <<
82 properties: <<
83 clocks: <<
84 minItems: 2 <<
85 maxItems: 4 <<
86 description: Phandle to two (Torrent) <<
87 the inputs to refclk_dig <<
88 <<
89 "#clock-cells": <<
90 const: 0 <<
91 <<
92 clock-output-names: <<
93 maxItems: 1 <<
94 <<
95 assigned-clocks: <<
96 maxItems: 1 <<
97 <<
98 assigned-clock-parents: <<
99 maxItems: 1 <<
100 <<
101 required: <<
102 - clocks <<
103 - "#clock-cells" <<
104 - assigned-clocks <<
105 - assigned-clock-parents <<
106 <<
107 ti,scm: <<
108 $ref: /schemas/types.yaml#/definitions/pha <<
109 description: | <<
110 phandle to System Control Module for sys <<
111 <<
112 patternProperties: 76 patternProperties:
113 "^pll[0|1]-refclk$": 77 "^pll[0|1]-refclk$":
114 type: object 78 type: object
115 additionalProperties: false <<
116 description: | 79 description: |
117 WIZ node should have subnodes for each o 80 WIZ node should have subnodes for each of the PLLs present in
118 the SERDES. 81 the SERDES.
119 deprecated: true <<
120 properties: 82 properties:
121 clocks: 83 clocks:
122 maxItems: 2 84 maxItems: 2
123 description: Phandle to clock nodes re 85 description: Phandle to clock nodes representing the two inputs to PLL.
124 86
125 "#clock-cells": 87 "#clock-cells":
126 const: 0 88 const: 0
127 89
128 clock-output-names: <<
129 maxItems: 1 <<
130 <<
131 assigned-clocks: 90 assigned-clocks:
132 maxItems: 1 91 maxItems: 1
133 92
134 assigned-clock-parents: 93 assigned-clock-parents:
135 maxItems: 1 94 maxItems: 1
136 95
137 required: 96 required:
138 - clocks 97 - clocks
139 - "#clock-cells" 98 - "#clock-cells"
140 - assigned-clocks 99 - assigned-clocks
141 - assigned-clock-parents 100 - assigned-clock-parents
142 101
143 "^cmn-refclk1?-dig-div$": 102 "^cmn-refclk1?-dig-div$":
144 type: object 103 type: object
145 additionalProperties: false <<
146 description: 104 description:
147 WIZ node should have subnodes for each o 105 WIZ node should have subnodes for each of the PMA common refclock
148 provided by the SERDES. 106 provided by the SERDES.
149 deprecated: true <<
150 properties: 107 properties:
151 clocks: 108 clocks:
152 maxItems: 1 109 maxItems: 1
153 description: Phandle to the clock node 110 description: Phandle to the clock node representing the input to the
154 divider clock. 111 divider clock.
155 112
156 "#clock-cells": 113 "#clock-cells":
157 const: 0 114 const: 0
158 115
159 clock-output-names: !! 116 required:
>> 117 - clocks
>> 118 - "#clock-cells"
>> 119
>> 120 "^refclk-dig$":
>> 121 type: object
>> 122 description: |
>> 123 WIZ node should have subnode for refclk_dig to select the reference
>> 124 clock source for the reference clock used in the PHY and PMA digital
>> 125 logic.
>> 126 properties:
>> 127 clocks:
>> 128 minItems: 2
>> 129 maxItems: 4
>> 130 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
>> 131 the inputs to refclk_dig
>> 132
>> 133 "#clock-cells":
>> 134 const: 0
>> 135
>> 136 assigned-clocks:
>> 137 maxItems: 1
>> 138
>> 139 assigned-clock-parents:
160 maxItems: 1 140 maxItems: 1
161 141
162 required: 142 required:
163 - clocks 143 - clocks
164 - "#clock-cells" 144 - "#clock-cells"
>> 145 - assigned-clocks
>> 146 - assigned-clock-parents
165 147
166 "^serdes@[0-9a-f]+$": 148 "^serdes@[0-9a-f]+$":
167 type: object 149 type: object
168 description: | 150 description: |
169 WIZ node should have '1' subnode for the 151 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra 152 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
171 bindings specified in 153 bindings specified in
172 Documentation/devicetree/bindings/phy/ph !! 154 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
173 Torrent SERDES should follow the binding 155 Torrent SERDES should follow the bindings specified in
174 Documentation/devicetree/bindings/phy/ph 156 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
175 157
176 required: 158 required:
177 - compatible 159 - compatible
178 - power-domains 160 - power-domains
179 - clocks 161 - clocks
180 - clock-names 162 - clock-names
181 - num-lanes 163 - num-lanes
182 - "#address-cells" 164 - "#address-cells"
183 - "#size-cells" 165 - "#size-cells"
184 - "#reset-cells" 166 - "#reset-cells"
185 - ranges 167 - ranges
186 168
187 allOf: <<
188 - if: <<
189 properties: <<
190 compatible: <<
191 contains: <<
192 const: ti,j7200-wiz-10g <<
193 then: <<
194 required: <<
195 - ti,scm <<
196 <<
197 additionalProperties: false 169 additionalProperties: false
198 170
199 examples: 171 examples:
200 - | 172 - |
201 #include <dt-bindings/soc/ti,sci_pm_domain 173 #include <dt-bindings/soc/ti,sci_pm_domain.h>
202 174
203 wiz@5000000 { 175 wiz@5000000 {
204 compatible = "ti,j721e-wiz-16g"; 176 compatible = "ti,j721e-wiz-16g";
205 #address-cells = <1>; 177 #address-cells = <1>;
206 #size-cells = <1>; 178 #size-cells = <1>;
207 power-domains = <&k3_pds 292 TI_SCI 179 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
208 clocks = <&k3_clks 292 5>, <&k3_clk 180 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
209 clock-names = "fck", "core_ref_clk" 181 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
210 assigned-clocks = <&k3_clks 292 11> 182 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 183 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
212 num-lanes = <2>; 184 num-lanes = <2>;
213 #reset-cells = <1>; 185 #reset-cells = <1>;
214 ranges = <0x5000000 0x5000000 0x100 186 ranges = <0x5000000 0x5000000 0x10000>;
215 187
216 pll0-refclk { 188 pll0-refclk {
217 clocks = <&k3_clks 293 13>, 189 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
218 #clock-cells = <0>; 190 #clock-cells = <0>;
219 assigned-clocks = <&wiz1_pll 191 assigned-clocks = <&wiz1_pll0_refclk>;
220 assigned-clock-parents = <&k 192 assigned-clock-parents = <&k3_clks 293 13>;
221 }; 193 };
222 194
223 pll1-refclk { 195 pll1-refclk {
224 clocks = <&k3_clks 293 0>, < 196 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
225 #clock-cells = <0>; 197 #clock-cells = <0>;
226 assigned-clocks = <&wiz1_pll 198 assigned-clocks = <&wiz1_pll1_refclk>;
227 assigned-clock-parents = <&k 199 assigned-clock-parents = <&k3_clks 293 0>;
228 }; 200 };
229 201
230 cmn-refclk-dig-div { 202 cmn-refclk-dig-div {
231 clocks = <&wiz1_refclk_dig>; 203 clocks = <&wiz1_refclk_dig>;
232 #clock-cells = <0>; 204 #clock-cells = <0>;
233 }; 205 };
234 206
235 cmn-refclk1-dig-div { 207 cmn-refclk1-dig-div {
236 clocks = <&wiz1_pll1_refclk> 208 clocks = <&wiz1_pll1_refclk>;
237 #clock-cells = <0>; 209 #clock-cells = <0>;
238 }; 210 };
239 211
240 refclk-dig { 212 refclk-dig {
241 clocks = <&k3_clks 292 11>, 213 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
242 <&dummy_cmn_refclk>, 214 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
243 #clock-cells = <0>; 215 #clock-cells = <0>;
244 assigned-clocks = <&wiz0_ref 216 assigned-clocks = <&wiz0_refclk_dig>;
245 assigned-clock-parents = <&k 217 assigned-clock-parents = <&k3_clks 292 11>;
246 }; 218 };
247 219
248 serdes@5000000 { 220 serdes@5000000 {
249 compatible = "ti,sierra-phy- !! 221 compatible = "cdns,ti,sierra-phy-t0";
250 reg-names = "serdes"; 222 reg-names = "serdes";
251 reg = <0x5000000 0x10000>; 223 reg = <0x5000000 0x10000>;
252 #address-cells = <1>; 224 #address-cells = <1>;
253 #size-cells = <0>; 225 #size-cells = <0>;
254 resets = <&serdes_wiz0 0>; 226 resets = <&serdes_wiz0 0>;
255 reset-names = "sierra_reset" 227 reset-names = "sierra_reset";
256 clocks = <&wiz0_cmn_refclk_d 228 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
257 clock-names = "cmn_refclk_di 229 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
258 }; 230 };
259 }; 231 };
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