1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorpo 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- !! 5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: TI J721E WIZ (SERDES Wrapper) 8 title: TI J721E WIZ (SERDES Wrapper)
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 enum: 15 enum:
16 - ti,j721e-wiz-16g 16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g 17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g <<
19 - ti,am64-wiz-10g 18 - ti,am64-wiz-10g
20 - ti,j7200-wiz-10g <<
21 - ti,j784s4-wiz-10g <<
22 19
23 power-domains: 20 power-domains:
24 maxItems: 1 21 maxItems: 1
25 22
26 clocks: 23 clocks:
27 minItems: 3 !! 24 maxItems: 3
28 maxItems: 4 <<
29 description: clock-specifier to represent 25 description: clock-specifier to represent input to the WIZ
30 26
31 clock-names: 27 clock-names:
32 minItems: 3 <<
33 items: 28 items:
34 - const: fck 29 - const: fck
35 - const: core_ref_clk 30 - const: core_ref_clk
36 - const: ext_ref_clk 31 - const: ext_ref_clk
37 - const: core_ref1_clk <<
38 32
39 num-lanes: 33 num-lanes:
40 minimum: 1 34 minimum: 1
41 maximum: 4 35 maximum: 4
42 36
43 "#address-cells": 37 "#address-cells":
44 const: 1 38 const: 1
45 39
46 "#size-cells": 40 "#size-cells":
47 const: 1 41 const: 1
48 42
49 "#reset-cells": 43 "#reset-cells":
50 const: 1 44 const: 1
51 45
52 "#clock-cells": 46 "#clock-cells":
53 const: 1 47 const: 1
54 48
55 ranges: true 49 ranges: true
56 50
>> 51 assigned-clocks:
>> 52 minItems: 1
>> 53 maxItems: 2
>> 54
>> 55 assigned-clock-parents:
>> 56 minItems: 1
>> 57 maxItems: 2
>> 58
>> 59 assigned-clock-rates:
>> 60 minItems: 1
>> 61 maxItems: 2
>> 62
57 typec-dir-gpios: 63 typec-dir-gpios:
58 maxItems: 1 64 maxItems: 1
59 description: 65 description:
60 GPIO to signal Type-C cable orientation 66 GPIO to signal Type-C cable orientation for lane swap.
61 If GPIO is active, lane 0 and lane 1 of 67 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
62 achieve the functionality of an external !! 68 achieve the funtionality of an external type-C plug flip mux.
63 69
64 typec-dir-debounce-ms: 70 typec-dir-debounce-ms:
65 minimum: 100 71 minimum: 100
66 maximum: 1000 72 maximum: 1000
67 default: 100 73 default: 100
68 description: 74 description:
69 Number of milliseconds to wait before sa 75 Number of milliseconds to wait before sampling typec-dir-gpio.
70 If not specified, the default debounce o 76 If not specified, the default debounce of 100ms will be used.
71 Type-C spec states minimum CC pin deboun 77 Type-C spec states minimum CC pin debounce of 100 ms and maximum
72 of 200 ms. However, some solutions might 78 of 200 ms. However, some solutions might need more than 200 ms.
73 79
74 refclk-dig: 80 refclk-dig:
75 type: object 81 type: object
76 additionalProperties: false <<
77 description: | 82 description: |
78 WIZ node should have subnode for refclk_ 83 WIZ node should have subnode for refclk_dig to select the reference
79 clock source for the reference clock use 84 clock source for the reference clock used in the PHY and PMA digital
80 logic. 85 logic.
81 deprecated: true <<
82 properties: 86 properties:
83 clocks: 87 clocks:
84 minItems: 2 88 minItems: 2
85 maxItems: 4 89 maxItems: 4
86 description: Phandle to two (Torrent) 90 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
87 the inputs to refclk_dig 91 the inputs to refclk_dig
88 92
89 "#clock-cells": 93 "#clock-cells":
90 const: 0 94 const: 0
91 95
92 clock-output-names: <<
93 maxItems: 1 <<
94 <<
95 assigned-clocks: 96 assigned-clocks:
96 maxItems: 1 97 maxItems: 1
97 98
98 assigned-clock-parents: 99 assigned-clock-parents:
99 maxItems: 1 100 maxItems: 1
100 101
101 required: 102 required:
102 - clocks 103 - clocks
103 - "#clock-cells" 104 - "#clock-cells"
104 - assigned-clocks 105 - assigned-clocks
105 - assigned-clock-parents 106 - assigned-clock-parents
106 107
107 ti,scm: <<
108 $ref: /schemas/types.yaml#/definitions/pha <<
109 description: | <<
110 phandle to System Control Module for sys <<
111 <<
112 patternProperties: 108 patternProperties:
113 "^pll[0|1]-refclk$": 109 "^pll[0|1]-refclk$":
114 type: object 110 type: object
115 additionalProperties: false <<
116 description: | 111 description: |
117 WIZ node should have subnodes for each o 112 WIZ node should have subnodes for each of the PLLs present in
118 the SERDES. 113 the SERDES.
119 deprecated: true <<
120 properties: 114 properties:
121 clocks: 115 clocks:
122 maxItems: 2 116 maxItems: 2
123 description: Phandle to clock nodes re 117 description: Phandle to clock nodes representing the two inputs to PLL.
124 118
125 "#clock-cells": 119 "#clock-cells":
126 const: 0 120 const: 0
127 121
128 clock-output-names: <<
129 maxItems: 1 <<
130 <<
131 assigned-clocks: 122 assigned-clocks:
132 maxItems: 1 123 maxItems: 1
133 124
134 assigned-clock-parents: 125 assigned-clock-parents:
135 maxItems: 1 126 maxItems: 1
136 127
137 required: 128 required:
138 - clocks 129 - clocks
139 - "#clock-cells" 130 - "#clock-cells"
140 - assigned-clocks 131 - assigned-clocks
141 - assigned-clock-parents 132 - assigned-clock-parents
142 133
143 "^cmn-refclk1?-dig-div$": 134 "^cmn-refclk1?-dig-div$":
144 type: object 135 type: object
145 additionalProperties: false <<
146 description: 136 description:
147 WIZ node should have subnodes for each o 137 WIZ node should have subnodes for each of the PMA common refclock
148 provided by the SERDES. 138 provided by the SERDES.
149 deprecated: true <<
150 properties: 139 properties:
151 clocks: 140 clocks:
152 maxItems: 1 141 maxItems: 1
153 description: Phandle to the clock node 142 description: Phandle to the clock node representing the input to the
154 divider clock. 143 divider clock.
155 144
156 "#clock-cells": 145 "#clock-cells":
157 const: 0 146 const: 0
158 147
159 clock-output-names: <<
160 maxItems: 1 <<
161 <<
162 required: 148 required:
163 - clocks 149 - clocks
164 - "#clock-cells" 150 - "#clock-cells"
165 151
166 "^serdes@[0-9a-f]+$": 152 "^serdes@[0-9a-f]+$":
167 type: object 153 type: object
168 description: | 154 description: |
169 WIZ node should have '1' subnode for the 155 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra 156 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
171 bindings specified in 157 bindings specified in
172 Documentation/devicetree/bindings/phy/ph 158 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
173 Torrent SERDES should follow the binding 159 Torrent SERDES should follow the bindings specified in
174 Documentation/devicetree/bindings/phy/ph 160 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
175 161
176 required: 162 required:
177 - compatible 163 - compatible
178 - power-domains 164 - power-domains
179 - clocks 165 - clocks
180 - clock-names 166 - clock-names
181 - num-lanes 167 - num-lanes
182 - "#address-cells" 168 - "#address-cells"
183 - "#size-cells" 169 - "#size-cells"
184 - "#reset-cells" 170 - "#reset-cells"
185 - ranges 171 - ranges
186 <<
187 allOf: <<
188 - if: <<
189 properties: <<
190 compatible: <<
191 contains: <<
192 const: ti,j7200-wiz-10g <<
193 then: <<
194 required: <<
195 - ti,scm <<
196 172
197 additionalProperties: false 173 additionalProperties: false
198 174
199 examples: 175 examples:
200 - | 176 - |
201 #include <dt-bindings/soc/ti,sci_pm_domain 177 #include <dt-bindings/soc/ti,sci_pm_domain.h>
202 178
203 wiz@5000000 { 179 wiz@5000000 {
204 compatible = "ti,j721e-wiz-16g"; 180 compatible = "ti,j721e-wiz-16g";
205 #address-cells = <1>; 181 #address-cells = <1>;
206 #size-cells = <1>; 182 #size-cells = <1>;
207 power-domains = <&k3_pds 292 TI_SCI 183 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
208 clocks = <&k3_clks 292 5>, <&k3_clk 184 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
209 clock-names = "fck", "core_ref_clk" 185 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
210 assigned-clocks = <&k3_clks 292 11> 186 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 187 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
212 num-lanes = <2>; 188 num-lanes = <2>;
213 #reset-cells = <1>; 189 #reset-cells = <1>;
214 ranges = <0x5000000 0x5000000 0x100 190 ranges = <0x5000000 0x5000000 0x10000>;
215 191
216 pll0-refclk { 192 pll0-refclk {
217 clocks = <&k3_clks 293 13>, 193 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
218 #clock-cells = <0>; 194 #clock-cells = <0>;
219 assigned-clocks = <&wiz1_pll 195 assigned-clocks = <&wiz1_pll0_refclk>;
220 assigned-clock-parents = <&k 196 assigned-clock-parents = <&k3_clks 293 13>;
221 }; 197 };
222 198
223 pll1-refclk { 199 pll1-refclk {
224 clocks = <&k3_clks 293 0>, < 200 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
225 #clock-cells = <0>; 201 #clock-cells = <0>;
226 assigned-clocks = <&wiz1_pll 202 assigned-clocks = <&wiz1_pll1_refclk>;
227 assigned-clock-parents = <&k 203 assigned-clock-parents = <&k3_clks 293 0>;
228 }; 204 };
229 205
230 cmn-refclk-dig-div { 206 cmn-refclk-dig-div {
231 clocks = <&wiz1_refclk_dig>; 207 clocks = <&wiz1_refclk_dig>;
232 #clock-cells = <0>; 208 #clock-cells = <0>;
233 }; 209 };
234 210
235 cmn-refclk1-dig-div { 211 cmn-refclk1-dig-div {
236 clocks = <&wiz1_pll1_refclk> 212 clocks = <&wiz1_pll1_refclk>;
237 #clock-cells = <0>; 213 #clock-cells = <0>;
238 }; 214 };
239 215
240 refclk-dig { 216 refclk-dig {
241 clocks = <&k3_clks 292 11>, 217 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
242 <&dummy_cmn_refclk>, 218 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
243 #clock-cells = <0>; 219 #clock-cells = <0>;
244 assigned-clocks = <&wiz0_ref 220 assigned-clocks = <&wiz0_refclk_dig>;
245 assigned-clock-parents = <&k 221 assigned-clock-parents = <&k3_clks 292 11>;
246 }; 222 };
247 223
248 serdes@5000000 { 224 serdes@5000000 {
249 compatible = "ti,sierra-phy- 225 compatible = "ti,sierra-phy-t0";
250 reg-names = "serdes"; 226 reg-names = "serdes";
251 reg = <0x5000000 0x10000>; 227 reg = <0x5000000 0x10000>;
252 #address-cells = <1>; 228 #address-cells = <1>;
253 #size-cells = <0>; 229 #size-cells = <0>;
254 resets = <&serdes_wiz0 0>; 230 resets = <&serdes_wiz0 0>;
255 reset-names = "sierra_reset" 231 reset-names = "sierra_reset";
256 clocks = <&wiz0_cmn_refclk_d 232 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
257 clock-names = "cmn_refclk_di 233 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
258 }; 234 };
259 }; 235 };
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