1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorpo 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- !! 5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: TI J721E WIZ (SERDES Wrapper) 8 title: TI J721E WIZ (SERDES Wrapper)
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 enum: 15 enum:
16 - ti,j721e-wiz-16g 16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g 17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g <<
19 - ti,am64-wiz-10g <<
20 - ti,j7200-wiz-10g <<
21 - ti,j784s4-wiz-10g <<
22 18
23 power-domains: 19 power-domains:
24 maxItems: 1 20 maxItems: 1
25 21
26 clocks: 22 clocks:
27 minItems: 3 !! 23 maxItems: 3
28 maxItems: 4 <<
29 description: clock-specifier to represent 24 description: clock-specifier to represent input to the WIZ
30 25
31 clock-names: 26 clock-names:
32 minItems: 3 <<
33 items: 27 items:
34 - const: fck 28 - const: fck
35 - const: core_ref_clk 29 - const: core_ref_clk
36 - const: ext_ref_clk 30 - const: ext_ref_clk
37 - const: core_ref1_clk <<
38 31
39 num-lanes: 32 num-lanes:
40 minimum: 1 33 minimum: 1
41 maximum: 4 34 maximum: 4
42 35
43 "#address-cells": 36 "#address-cells":
44 const: 1 37 const: 1
45 38
46 "#size-cells": 39 "#size-cells":
47 const: 1 40 const: 1
48 41
49 "#reset-cells": 42 "#reset-cells":
50 const: 1 43 const: 1
51 44
52 "#clock-cells": <<
53 const: 1 <<
54 <<
55 ranges: true 45 ranges: true
56 46
>> 47 assigned-clocks:
>> 48 maxItems: 2
>> 49
>> 50 assigned-clock-parents:
>> 51 maxItems: 2
>> 52
57 typec-dir-gpios: 53 typec-dir-gpios:
58 maxItems: 1 54 maxItems: 1
59 description: 55 description:
60 GPIO to signal Type-C cable orientation 56 GPIO to signal Type-C cable orientation for lane swap.
61 If GPIO is active, lane 0 and lane 1 of 57 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
62 achieve the functionality of an external !! 58 achieve the funtionality of an external type-C plug flip mux.
63 59
64 typec-dir-debounce-ms: 60 typec-dir-debounce-ms:
65 minimum: 100 61 minimum: 100
66 maximum: 1000 62 maximum: 1000
67 default: 100 63 default: 100
68 description: 64 description:
69 Number of milliseconds to wait before sa 65 Number of milliseconds to wait before sampling typec-dir-gpio.
70 If not specified, the default debounce o 66 If not specified, the default debounce of 100ms will be used.
71 Type-C spec states minimum CC pin deboun 67 Type-C spec states minimum CC pin debounce of 100 ms and maximum
72 of 200 ms. However, some solutions might 68 of 200 ms. However, some solutions might need more than 200 ms.
73 69
74 refclk-dig: <<
75 type: object <<
76 additionalProperties: false <<
77 description: | <<
78 WIZ node should have subnode for refclk_ <<
79 clock source for the reference clock use <<
80 logic. <<
81 deprecated: true <<
82 properties: <<
83 clocks: <<
84 minItems: 2 <<
85 maxItems: 4 <<
86 description: Phandle to two (Torrent) <<
87 the inputs to refclk_dig <<
88 <<
89 "#clock-cells": <<
90 const: 0 <<
91 <<
92 clock-output-names: <<
93 maxItems: 1 <<
94 <<
95 assigned-clocks: <<
96 maxItems: 1 <<
97 <<
98 assigned-clock-parents: <<
99 maxItems: 1 <<
100 <<
101 required: <<
102 - clocks <<
103 - "#clock-cells" <<
104 - assigned-clocks <<
105 - assigned-clock-parents <<
106 <<
107 ti,scm: <<
108 $ref: /schemas/types.yaml#/definitions/pha <<
109 description: | <<
110 phandle to System Control Module for sys <<
111 <<
112 patternProperties: 70 patternProperties:
113 "^pll[0|1]-refclk$": 71 "^pll[0|1]-refclk$":
114 type: object 72 type: object
115 additionalProperties: false <<
116 description: | 73 description: |
117 WIZ node should have subnodes for each o 74 WIZ node should have subnodes for each of the PLLs present in
118 the SERDES. 75 the SERDES.
119 deprecated: true <<
120 properties: 76 properties:
121 clocks: 77 clocks:
122 maxItems: 2 78 maxItems: 2
123 description: Phandle to clock nodes re 79 description: Phandle to clock nodes representing the two inputs to PLL.
124 80
125 "#clock-cells": 81 "#clock-cells":
126 const: 0 82 const: 0
127 83
128 clock-output-names: <<
129 maxItems: 1 <<
130 <<
131 assigned-clocks: 84 assigned-clocks:
132 maxItems: 1 85 maxItems: 1
133 86
134 assigned-clock-parents: 87 assigned-clock-parents:
135 maxItems: 1 88 maxItems: 1
136 89
137 required: 90 required:
138 - clocks 91 - clocks
139 - "#clock-cells" 92 - "#clock-cells"
140 - assigned-clocks 93 - assigned-clocks
141 - assigned-clock-parents 94 - assigned-clock-parents
142 95
143 "^cmn-refclk1?-dig-div$": 96 "^cmn-refclk1?-dig-div$":
144 type: object 97 type: object
145 additionalProperties: false <<
146 description: 98 description:
147 WIZ node should have subnodes for each o 99 WIZ node should have subnodes for each of the PMA common refclock
148 provided by the SERDES. 100 provided by the SERDES.
149 deprecated: true <<
150 properties: 101 properties:
151 clocks: 102 clocks:
152 maxItems: 1 103 maxItems: 1
153 description: Phandle to the clock node 104 description: Phandle to the clock node representing the input to the
154 divider clock. 105 divider clock.
155 106
156 "#clock-cells": 107 "#clock-cells":
157 const: 0 108 const: 0
158 109
159 clock-output-names: !! 110 required:
>> 111 - clocks
>> 112 - "#clock-cells"
>> 113
>> 114 "^refclk-dig$":
>> 115 type: object
>> 116 description: |
>> 117 WIZ node should have subnode for refclk_dig to select the reference
>> 118 clock source for the reference clock used in the PHY and PMA digital
>> 119 logic.
>> 120 properties:
>> 121 clocks:
>> 122 maxItems: 4
>> 123 description: Phandle to four clock nodes representing the inputs to
>> 124 refclk_dig
>> 125
>> 126 "#clock-cells":
>> 127 const: 0
>> 128
>> 129 assigned-clocks:
>> 130 maxItems: 1
>> 131
>> 132 assigned-clock-parents:
160 maxItems: 1 133 maxItems: 1
161 134
162 required: 135 required:
163 - clocks 136 - clocks
164 - "#clock-cells" 137 - "#clock-cells"
>> 138 - assigned-clocks
>> 139 - assigned-clock-parents
165 140
166 "^serdes@[0-9a-f]+$": 141 "^serdes@[0-9a-f]+$":
167 type: object 142 type: object
168 description: | 143 description: |
169 WIZ node should have '1' subnode for the 144 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra 145 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
171 bindings specified in 146 bindings specified in
172 Documentation/devicetree/bindings/phy/ph !! 147 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
173 Torrent SERDES should follow the binding 148 Torrent SERDES should follow the bindings specified in
174 Documentation/devicetree/bindings/phy/ph 149 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
175 150
176 required: 151 required:
177 - compatible 152 - compatible
178 - power-domains 153 - power-domains
179 - clocks 154 - clocks
180 - clock-names 155 - clock-names
181 - num-lanes 156 - num-lanes
182 - "#address-cells" 157 - "#address-cells"
183 - "#size-cells" 158 - "#size-cells"
184 - "#reset-cells" 159 - "#reset-cells"
185 - ranges 160 - ranges
186 161
187 allOf: <<
188 - if: <<
189 properties: <<
190 compatible: <<
191 contains: <<
192 const: ti,j7200-wiz-10g <<
193 then: <<
194 required: <<
195 - ti,scm <<
196 <<
197 additionalProperties: false 162 additionalProperties: false
198 163
199 examples: 164 examples:
200 - | 165 - |
201 #include <dt-bindings/soc/ti,sci_pm_domain 166 #include <dt-bindings/soc/ti,sci_pm_domain.h>
202 167
203 wiz@5000000 { 168 wiz@5000000 {
204 compatible = "ti,j721e-wiz-16g"; 169 compatible = "ti,j721e-wiz-16g";
205 #address-cells = <1>; 170 #address-cells = <1>;
206 #size-cells = <1>; 171 #size-cells = <1>;
207 power-domains = <&k3_pds 292 TI_SCI 172 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
208 clocks = <&k3_clks 292 5>, <&k3_clk 173 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
209 clock-names = "fck", "core_ref_clk" 174 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
210 assigned-clocks = <&k3_clks 292 11> 175 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 176 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
212 num-lanes = <2>; 177 num-lanes = <2>;
213 #reset-cells = <1>; 178 #reset-cells = <1>;
214 ranges = <0x5000000 0x5000000 0x100 179 ranges = <0x5000000 0x5000000 0x10000>;
215 180
216 pll0-refclk { 181 pll0-refclk {
217 clocks = <&k3_clks 293 13>, 182 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
218 #clock-cells = <0>; 183 #clock-cells = <0>;
219 assigned-clocks = <&wiz1_pll 184 assigned-clocks = <&wiz1_pll0_refclk>;
220 assigned-clock-parents = <&k 185 assigned-clock-parents = <&k3_clks 293 13>;
221 }; 186 };
222 187
223 pll1-refclk { 188 pll1-refclk {
224 clocks = <&k3_clks 293 0>, < 189 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
225 #clock-cells = <0>; 190 #clock-cells = <0>;
226 assigned-clocks = <&wiz1_pll 191 assigned-clocks = <&wiz1_pll1_refclk>;
227 assigned-clock-parents = <&k 192 assigned-clock-parents = <&k3_clks 293 0>;
228 }; 193 };
229 194
230 cmn-refclk-dig-div { 195 cmn-refclk-dig-div {
231 clocks = <&wiz1_refclk_dig>; 196 clocks = <&wiz1_refclk_dig>;
232 #clock-cells = <0>; 197 #clock-cells = <0>;
233 }; 198 };
234 199
235 cmn-refclk1-dig-div { 200 cmn-refclk1-dig-div {
236 clocks = <&wiz1_pll1_refclk> 201 clocks = <&wiz1_pll1_refclk>;
237 #clock-cells = <0>; 202 #clock-cells = <0>;
238 }; 203 };
239 204
240 refclk-dig { 205 refclk-dig {
241 clocks = <&k3_clks 292 11>, !! 206 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
242 <&dummy_cmn_refclk>, <<
243 #clock-cells = <0>; 207 #clock-cells = <0>;
244 assigned-clocks = <&wiz0_ref 208 assigned-clocks = <&wiz0_refclk_dig>;
245 assigned-clock-parents = <&k 209 assigned-clock-parents = <&k3_clks 292 11>;
246 }; 210 };
247 211
248 serdes@5000000 { 212 serdes@5000000 {
249 compatible = "ti,sierra-phy- !! 213 compatible = "cdns,ti,sierra-phy-t0";
250 reg-names = "serdes"; 214 reg-names = "serdes";
251 reg = <0x5000000 0x10000>; 215 reg = <0x5000000 0x10000>;
252 #address-cells = <1>; 216 #address-cells = <1>;
253 #size-cells = <0>; 217 #size-cells = <0>;
254 resets = <&serdes_wiz0 0>; 218 resets = <&serdes_wiz0 0>;
255 reset-names = "sierra_reset" 219 reset-names = "sierra_reset";
256 clocks = <&wiz0_cmn_refclk_d 220 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
257 clock-names = "cmn_refclk_di 221 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
258 }; 222 };
259 }; 223 };
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