1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorpo 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- !! 5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: TI J721E WIZ (SERDES Wrapper) 8 title: TI J721E WIZ (SERDES Wrapper)
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 enum: 15 enum:
16 - ti,j721e-wiz-16g 16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g 17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g <<
19 - ti,am64-wiz-10g 18 - ti,am64-wiz-10g
20 - ti,j7200-wiz-10g 19 - ti,j7200-wiz-10g
21 - ti,j784s4-wiz-10g <<
22 20
23 power-domains: 21 power-domains:
24 maxItems: 1 22 maxItems: 1
25 23
26 clocks: 24 clocks:
27 minItems: 3 25 minItems: 3
28 maxItems: 4 26 maxItems: 4
29 description: clock-specifier to represent 27 description: clock-specifier to represent input to the WIZ
30 28
31 clock-names: 29 clock-names:
32 minItems: 3 30 minItems: 3
33 items: 31 items:
34 - const: fck 32 - const: fck
35 - const: core_ref_clk 33 - const: core_ref_clk
36 - const: ext_ref_clk 34 - const: ext_ref_clk
37 - const: core_ref1_clk 35 - const: core_ref1_clk
38 36
39 num-lanes: 37 num-lanes:
40 minimum: 1 38 minimum: 1
41 maximum: 4 39 maximum: 4
42 40
43 "#address-cells": 41 "#address-cells":
44 const: 1 42 const: 1
45 43
46 "#size-cells": 44 "#size-cells":
47 const: 1 45 const: 1
48 46
49 "#reset-cells": 47 "#reset-cells":
50 const: 1 48 const: 1
51 49
52 "#clock-cells": 50 "#clock-cells":
53 const: 1 51 const: 1
54 52
55 ranges: true 53 ranges: true
56 54
>> 55 assigned-clocks:
>> 56 minItems: 1
>> 57 maxItems: 2
>> 58
>> 59 assigned-clock-parents:
>> 60 minItems: 1
>> 61 maxItems: 2
>> 62
>> 63 assigned-clock-rates:
>> 64 minItems: 1
>> 65 maxItems: 2
>> 66
57 typec-dir-gpios: 67 typec-dir-gpios:
58 maxItems: 1 68 maxItems: 1
59 description: 69 description:
60 GPIO to signal Type-C cable orientation 70 GPIO to signal Type-C cable orientation for lane swap.
61 If GPIO is active, lane 0 and lane 1 of 71 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
62 achieve the functionality of an external !! 72 achieve the funtionality of an external type-C plug flip mux.
63 73
64 typec-dir-debounce-ms: 74 typec-dir-debounce-ms:
65 minimum: 100 75 minimum: 100
66 maximum: 1000 76 maximum: 1000
67 default: 100 77 default: 100
68 description: 78 description:
69 Number of milliseconds to wait before sa 79 Number of milliseconds to wait before sampling typec-dir-gpio.
70 If not specified, the default debounce o 80 If not specified, the default debounce of 100ms will be used.
71 Type-C spec states minimum CC pin deboun 81 Type-C spec states minimum CC pin debounce of 100 ms and maximum
72 of 200 ms. However, some solutions might 82 of 200 ms. However, some solutions might need more than 200 ms.
73 83
74 refclk-dig: 84 refclk-dig:
75 type: object 85 type: object
76 additionalProperties: false 86 additionalProperties: false
77 description: | 87 description: |
78 WIZ node should have subnode for refclk_ 88 WIZ node should have subnode for refclk_dig to select the reference
79 clock source for the reference clock use 89 clock source for the reference clock used in the PHY and PMA digital
80 logic. 90 logic.
81 deprecated: true 91 deprecated: true
82 properties: 92 properties:
83 clocks: 93 clocks:
84 minItems: 2 94 minItems: 2
85 maxItems: 4 95 maxItems: 4
86 description: Phandle to two (Torrent) 96 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
87 the inputs to refclk_dig 97 the inputs to refclk_dig
88 98
89 "#clock-cells": 99 "#clock-cells":
90 const: 0 100 const: 0
91 101
92 clock-output-names: <<
93 maxItems: 1 <<
94 <<
95 assigned-clocks: 102 assigned-clocks:
96 maxItems: 1 103 maxItems: 1
97 104
98 assigned-clock-parents: 105 assigned-clock-parents:
99 maxItems: 1 106 maxItems: 1
100 107
101 required: 108 required:
102 - clocks 109 - clocks
103 - "#clock-cells" 110 - "#clock-cells"
104 - assigned-clocks 111 - assigned-clocks
105 - assigned-clock-parents 112 - assigned-clock-parents
106 113
107 ti,scm: 114 ti,scm:
108 $ref: /schemas/types.yaml#/definitions/pha 115 $ref: /schemas/types.yaml#/definitions/phandle
109 description: | 116 description: |
110 phandle to System Control Module for sys 117 phandle to System Control Module for syscon regmap access.
111 118
112 patternProperties: 119 patternProperties:
113 "^pll[0|1]-refclk$": 120 "^pll[0|1]-refclk$":
114 type: object 121 type: object
115 additionalProperties: false 122 additionalProperties: false
116 description: | 123 description: |
117 WIZ node should have subnodes for each o 124 WIZ node should have subnodes for each of the PLLs present in
118 the SERDES. 125 the SERDES.
119 deprecated: true 126 deprecated: true
120 properties: 127 properties:
121 clocks: 128 clocks:
122 maxItems: 2 129 maxItems: 2
123 description: Phandle to clock nodes re 130 description: Phandle to clock nodes representing the two inputs to PLL.
124 131
125 "#clock-cells": 132 "#clock-cells":
126 const: 0 133 const: 0
127 134
128 clock-output-names: <<
129 maxItems: 1 <<
130 <<
131 assigned-clocks: 135 assigned-clocks:
132 maxItems: 1 136 maxItems: 1
133 137
134 assigned-clock-parents: 138 assigned-clock-parents:
135 maxItems: 1 139 maxItems: 1
136 140
137 required: 141 required:
138 - clocks 142 - clocks
139 - "#clock-cells" 143 - "#clock-cells"
140 - assigned-clocks 144 - assigned-clocks
141 - assigned-clock-parents 145 - assigned-clock-parents
142 146
143 "^cmn-refclk1?-dig-div$": 147 "^cmn-refclk1?-dig-div$":
144 type: object 148 type: object
145 additionalProperties: false 149 additionalProperties: false
146 description: 150 description:
147 WIZ node should have subnodes for each o 151 WIZ node should have subnodes for each of the PMA common refclock
148 provided by the SERDES. 152 provided by the SERDES.
149 deprecated: true 153 deprecated: true
150 properties: 154 properties:
151 clocks: 155 clocks:
152 maxItems: 1 156 maxItems: 1
153 description: Phandle to the clock node 157 description: Phandle to the clock node representing the input to the
154 divider clock. 158 divider clock.
155 159
156 "#clock-cells": 160 "#clock-cells":
157 const: 0 161 const: 0
158 <<
159 clock-output-names: <<
160 maxItems: 1 <<
161 162
162 required: 163 required:
163 - clocks 164 - clocks
164 - "#clock-cells" 165 - "#clock-cells"
165 166
166 "^serdes@[0-9a-f]+$": 167 "^serdes@[0-9a-f]+$":
167 type: object 168 type: object
168 description: | 169 description: |
169 WIZ node should have '1' subnode for the 170 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra 171 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
171 bindings specified in 172 bindings specified in
172 Documentation/devicetree/bindings/phy/ph 173 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
173 Torrent SERDES should follow the binding 174 Torrent SERDES should follow the bindings specified in
174 Documentation/devicetree/bindings/phy/ph 175 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
175 176
176 required: 177 required:
177 - compatible 178 - compatible
178 - power-domains 179 - power-domains
179 - clocks 180 - clocks
180 - clock-names 181 - clock-names
181 - num-lanes 182 - num-lanes
182 - "#address-cells" 183 - "#address-cells"
183 - "#size-cells" 184 - "#size-cells"
184 - "#reset-cells" 185 - "#reset-cells"
185 - ranges 186 - ranges
186 187
187 allOf: 188 allOf:
188 - if: 189 - if:
189 properties: 190 properties:
190 compatible: 191 compatible:
191 contains: 192 contains:
192 const: ti,j7200-wiz-10g 193 const: ti,j7200-wiz-10g
193 then: 194 then:
194 required: 195 required:
195 - ti,scm 196 - ti,scm
196 197
197 additionalProperties: false 198 additionalProperties: false
198 199
199 examples: 200 examples:
200 - | 201 - |
201 #include <dt-bindings/soc/ti,sci_pm_domain 202 #include <dt-bindings/soc/ti,sci_pm_domain.h>
202 203
203 wiz@5000000 { 204 wiz@5000000 {
204 compatible = "ti,j721e-wiz-16g"; 205 compatible = "ti,j721e-wiz-16g";
205 #address-cells = <1>; 206 #address-cells = <1>;
206 #size-cells = <1>; 207 #size-cells = <1>;
207 power-domains = <&k3_pds 292 TI_SCI 208 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
208 clocks = <&k3_clks 292 5>, <&k3_clk 209 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
209 clock-names = "fck", "core_ref_clk" 210 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
210 assigned-clocks = <&k3_clks 292 11> 211 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 212 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
212 num-lanes = <2>; 213 num-lanes = <2>;
213 #reset-cells = <1>; 214 #reset-cells = <1>;
214 ranges = <0x5000000 0x5000000 0x100 215 ranges = <0x5000000 0x5000000 0x10000>;
215 216
216 pll0-refclk { 217 pll0-refclk {
217 clocks = <&k3_clks 293 13>, 218 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
218 #clock-cells = <0>; 219 #clock-cells = <0>;
219 assigned-clocks = <&wiz1_pll 220 assigned-clocks = <&wiz1_pll0_refclk>;
220 assigned-clock-parents = <&k 221 assigned-clock-parents = <&k3_clks 293 13>;
221 }; 222 };
222 223
223 pll1-refclk { 224 pll1-refclk {
224 clocks = <&k3_clks 293 0>, < 225 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
225 #clock-cells = <0>; 226 #clock-cells = <0>;
226 assigned-clocks = <&wiz1_pll 227 assigned-clocks = <&wiz1_pll1_refclk>;
227 assigned-clock-parents = <&k 228 assigned-clock-parents = <&k3_clks 293 0>;
228 }; 229 };
229 230
230 cmn-refclk-dig-div { 231 cmn-refclk-dig-div {
231 clocks = <&wiz1_refclk_dig>; 232 clocks = <&wiz1_refclk_dig>;
232 #clock-cells = <0>; 233 #clock-cells = <0>;
233 }; 234 };
234 235
235 cmn-refclk1-dig-div { 236 cmn-refclk1-dig-div {
236 clocks = <&wiz1_pll1_refclk> 237 clocks = <&wiz1_pll1_refclk>;
237 #clock-cells = <0>; 238 #clock-cells = <0>;
238 }; 239 };
239 240
240 refclk-dig { 241 refclk-dig {
241 clocks = <&k3_clks 292 11>, 242 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
242 <&dummy_cmn_refclk>, 243 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
243 #clock-cells = <0>; 244 #clock-cells = <0>;
244 assigned-clocks = <&wiz0_ref 245 assigned-clocks = <&wiz0_refclk_dig>;
245 assigned-clock-parents = <&k 246 assigned-clock-parents = <&k3_clks 292 11>;
246 }; 247 };
247 248
248 serdes@5000000 { 249 serdes@5000000 {
249 compatible = "ti,sierra-phy- 250 compatible = "ti,sierra-phy-t0";
250 reg-names = "serdes"; 251 reg-names = "serdes";
251 reg = <0x5000000 0x10000>; 252 reg = <0x5000000 0x10000>;
252 #address-cells = <1>; 253 #address-cells = <1>;
253 #size-cells = <0>; 254 #size-cells = <0>;
254 resets = <&serdes_wiz0 0>; 255 resets = <&serdes_wiz0 0>;
255 reset-names = "sierra_reset" 256 reset-names = "sierra_reset";
256 clocks = <&wiz0_cmn_refclk_d 257 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
257 clock-names = "cmn_refclk_di 258 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
258 }; 259 };
259 }; 260 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.