1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorpo 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- !! 5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: TI J721E WIZ (SERDES Wrapper) 8 title: TI J721E WIZ (SERDES Wrapper)
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 enum: 15 enum:
16 - ti,j721e-wiz-16g 16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g 17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g 18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g 19 - ti,am64-wiz-10g
20 - ti,j7200-wiz-10g 20 - ti,j7200-wiz-10g
21 - ti,j784s4-wiz-10g 21 - ti,j784s4-wiz-10g
22 22
23 power-domains: 23 power-domains:
24 maxItems: 1 24 maxItems: 1
25 25
26 clocks: 26 clocks:
27 minItems: 3 27 minItems: 3
28 maxItems: 4 28 maxItems: 4
29 description: clock-specifier to represent 29 description: clock-specifier to represent input to the WIZ
30 30
31 clock-names: 31 clock-names:
32 minItems: 3 32 minItems: 3
33 items: 33 items:
34 - const: fck 34 - const: fck
35 - const: core_ref_clk 35 - const: core_ref_clk
36 - const: ext_ref_clk 36 - const: ext_ref_clk
37 - const: core_ref1_clk 37 - const: core_ref1_clk
38 38
39 num-lanes: 39 num-lanes:
40 minimum: 1 40 minimum: 1
41 maximum: 4 41 maximum: 4
42 42
43 "#address-cells": 43 "#address-cells":
44 const: 1 44 const: 1
45 45
46 "#size-cells": 46 "#size-cells":
47 const: 1 47 const: 1
48 48
49 "#reset-cells": 49 "#reset-cells":
50 const: 1 50 const: 1
51 51
52 "#clock-cells": 52 "#clock-cells":
53 const: 1 53 const: 1
54 54
55 ranges: true 55 ranges: true
56 56
>> 57 assigned-clocks:
>> 58 minItems: 1
>> 59 maxItems: 2
>> 60
>> 61 assigned-clock-parents:
>> 62 minItems: 1
>> 63 maxItems: 2
>> 64
>> 65 assigned-clock-rates:
>> 66 minItems: 1
>> 67 maxItems: 2
>> 68
57 typec-dir-gpios: 69 typec-dir-gpios:
58 maxItems: 1 70 maxItems: 1
59 description: 71 description:
60 GPIO to signal Type-C cable orientation 72 GPIO to signal Type-C cable orientation for lane swap.
61 If GPIO is active, lane 0 and lane 1 of 73 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
62 achieve the functionality of an external !! 74 achieve the funtionality of an external type-C plug flip mux.
63 75
64 typec-dir-debounce-ms: 76 typec-dir-debounce-ms:
65 minimum: 100 77 minimum: 100
66 maximum: 1000 78 maximum: 1000
67 default: 100 79 default: 100
68 description: 80 description:
69 Number of milliseconds to wait before sa 81 Number of milliseconds to wait before sampling typec-dir-gpio.
70 If not specified, the default debounce o 82 If not specified, the default debounce of 100ms will be used.
71 Type-C spec states minimum CC pin deboun 83 Type-C spec states minimum CC pin debounce of 100 ms and maximum
72 of 200 ms. However, some solutions might 84 of 200 ms. However, some solutions might need more than 200 ms.
73 85
74 refclk-dig: 86 refclk-dig:
75 type: object 87 type: object
76 additionalProperties: false 88 additionalProperties: false
77 description: | 89 description: |
78 WIZ node should have subnode for refclk_ 90 WIZ node should have subnode for refclk_dig to select the reference
79 clock source for the reference clock use 91 clock source for the reference clock used in the PHY and PMA digital
80 logic. 92 logic.
81 deprecated: true 93 deprecated: true
82 properties: 94 properties:
83 clocks: 95 clocks:
84 minItems: 2 96 minItems: 2
85 maxItems: 4 97 maxItems: 4
86 description: Phandle to two (Torrent) 98 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
87 the inputs to refclk_dig 99 the inputs to refclk_dig
88 100
89 "#clock-cells": 101 "#clock-cells":
90 const: 0 102 const: 0
91 103
92 clock-output-names: <<
93 maxItems: 1 <<
94 <<
95 assigned-clocks: 104 assigned-clocks:
96 maxItems: 1 105 maxItems: 1
97 106
98 assigned-clock-parents: 107 assigned-clock-parents:
99 maxItems: 1 108 maxItems: 1
100 109
101 required: 110 required:
102 - clocks 111 - clocks
103 - "#clock-cells" 112 - "#clock-cells"
104 - assigned-clocks 113 - assigned-clocks
105 - assigned-clock-parents 114 - assigned-clock-parents
106 115
107 ti,scm: 116 ti,scm:
108 $ref: /schemas/types.yaml#/definitions/pha 117 $ref: /schemas/types.yaml#/definitions/phandle
109 description: | 118 description: |
110 phandle to System Control Module for sys 119 phandle to System Control Module for syscon regmap access.
111 120
112 patternProperties: 121 patternProperties:
113 "^pll[0|1]-refclk$": 122 "^pll[0|1]-refclk$":
114 type: object 123 type: object
115 additionalProperties: false 124 additionalProperties: false
116 description: | 125 description: |
117 WIZ node should have subnodes for each o 126 WIZ node should have subnodes for each of the PLLs present in
118 the SERDES. 127 the SERDES.
119 deprecated: true 128 deprecated: true
120 properties: 129 properties:
121 clocks: 130 clocks:
122 maxItems: 2 131 maxItems: 2
123 description: Phandle to clock nodes re 132 description: Phandle to clock nodes representing the two inputs to PLL.
124 133
125 "#clock-cells": 134 "#clock-cells":
126 const: 0 135 const: 0
127 136
128 clock-output-names: <<
129 maxItems: 1 <<
130 <<
131 assigned-clocks: 137 assigned-clocks:
132 maxItems: 1 138 maxItems: 1
133 139
134 assigned-clock-parents: 140 assigned-clock-parents:
135 maxItems: 1 141 maxItems: 1
136 142
137 required: 143 required:
138 - clocks 144 - clocks
139 - "#clock-cells" 145 - "#clock-cells"
140 - assigned-clocks 146 - assigned-clocks
141 - assigned-clock-parents 147 - assigned-clock-parents
142 148
143 "^cmn-refclk1?-dig-div$": 149 "^cmn-refclk1?-dig-div$":
144 type: object 150 type: object
145 additionalProperties: false 151 additionalProperties: false
146 description: 152 description:
147 WIZ node should have subnodes for each o 153 WIZ node should have subnodes for each of the PMA common refclock
148 provided by the SERDES. 154 provided by the SERDES.
149 deprecated: true 155 deprecated: true
150 properties: 156 properties:
151 clocks: 157 clocks:
152 maxItems: 1 158 maxItems: 1
153 description: Phandle to the clock node 159 description: Phandle to the clock node representing the input to the
154 divider clock. 160 divider clock.
155 161
156 "#clock-cells": 162 "#clock-cells":
157 const: 0 163 const: 0
158 <<
159 clock-output-names: <<
160 maxItems: 1 <<
161 164
162 required: 165 required:
163 - clocks 166 - clocks
164 - "#clock-cells" 167 - "#clock-cells"
165 168
166 "^serdes@[0-9a-f]+$": 169 "^serdes@[0-9a-f]+$":
167 type: object 170 type: object
168 description: | 171 description: |
169 WIZ node should have '1' subnode for the 172 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra 173 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
171 bindings specified in 174 bindings specified in
172 Documentation/devicetree/bindings/phy/ph 175 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
173 Torrent SERDES should follow the binding 176 Torrent SERDES should follow the bindings specified in
174 Documentation/devicetree/bindings/phy/ph 177 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
175 178
176 required: 179 required:
177 - compatible 180 - compatible
178 - power-domains 181 - power-domains
179 - clocks 182 - clocks
180 - clock-names 183 - clock-names
181 - num-lanes 184 - num-lanes
182 - "#address-cells" 185 - "#address-cells"
183 - "#size-cells" 186 - "#size-cells"
184 - "#reset-cells" 187 - "#reset-cells"
185 - ranges 188 - ranges
186 189
187 allOf: 190 allOf:
188 - if: 191 - if:
189 properties: 192 properties:
190 compatible: 193 compatible:
191 contains: 194 contains:
192 const: ti,j7200-wiz-10g 195 const: ti,j7200-wiz-10g
193 then: 196 then:
194 required: 197 required:
195 - ti,scm 198 - ti,scm
196 199
197 additionalProperties: false 200 additionalProperties: false
198 201
199 examples: 202 examples:
200 - | 203 - |
201 #include <dt-bindings/soc/ti,sci_pm_domain 204 #include <dt-bindings/soc/ti,sci_pm_domain.h>
202 205
203 wiz@5000000 { 206 wiz@5000000 {
204 compatible = "ti,j721e-wiz-16g"; 207 compatible = "ti,j721e-wiz-16g";
205 #address-cells = <1>; 208 #address-cells = <1>;
206 #size-cells = <1>; 209 #size-cells = <1>;
207 power-domains = <&k3_pds 292 TI_SCI 210 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
208 clocks = <&k3_clks 292 5>, <&k3_clk 211 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
209 clock-names = "fck", "core_ref_clk" 212 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
210 assigned-clocks = <&k3_clks 292 11> 213 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 214 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
212 num-lanes = <2>; 215 num-lanes = <2>;
213 #reset-cells = <1>; 216 #reset-cells = <1>;
214 ranges = <0x5000000 0x5000000 0x100 217 ranges = <0x5000000 0x5000000 0x10000>;
215 218
216 pll0-refclk { 219 pll0-refclk {
217 clocks = <&k3_clks 293 13>, 220 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
218 #clock-cells = <0>; 221 #clock-cells = <0>;
219 assigned-clocks = <&wiz1_pll 222 assigned-clocks = <&wiz1_pll0_refclk>;
220 assigned-clock-parents = <&k 223 assigned-clock-parents = <&k3_clks 293 13>;
221 }; 224 };
222 225
223 pll1-refclk { 226 pll1-refclk {
224 clocks = <&k3_clks 293 0>, < 227 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
225 #clock-cells = <0>; 228 #clock-cells = <0>;
226 assigned-clocks = <&wiz1_pll 229 assigned-clocks = <&wiz1_pll1_refclk>;
227 assigned-clock-parents = <&k 230 assigned-clock-parents = <&k3_clks 293 0>;
228 }; 231 };
229 232
230 cmn-refclk-dig-div { 233 cmn-refclk-dig-div {
231 clocks = <&wiz1_refclk_dig>; 234 clocks = <&wiz1_refclk_dig>;
232 #clock-cells = <0>; 235 #clock-cells = <0>;
233 }; 236 };
234 237
235 cmn-refclk1-dig-div { 238 cmn-refclk1-dig-div {
236 clocks = <&wiz1_pll1_refclk> 239 clocks = <&wiz1_pll1_refclk>;
237 #clock-cells = <0>; 240 #clock-cells = <0>;
238 }; 241 };
239 242
240 refclk-dig { 243 refclk-dig {
241 clocks = <&k3_clks 292 11>, 244 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
242 <&dummy_cmn_refclk>, 245 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
243 #clock-cells = <0>; 246 #clock-cells = <0>;
244 assigned-clocks = <&wiz0_ref 247 assigned-clocks = <&wiz0_refclk_dig>;
245 assigned-clock-parents = <&k 248 assigned-clock-parents = <&k3_clks 292 11>;
246 }; 249 };
247 250
248 serdes@5000000 { 251 serdes@5000000 {
249 compatible = "ti,sierra-phy- 252 compatible = "ti,sierra-phy-t0";
250 reg-names = "serdes"; 253 reg-names = "serdes";
251 reg = <0x5000000 0x10000>; 254 reg = <0x5000000 0x10000>;
252 #address-cells = <1>; 255 #address-cells = <1>;
253 #size-cells = <0>; 256 #size-cells = <0>;
254 resets = <&serdes_wiz0 0>; 257 resets = <&serdes_wiz0 0>;
255 reset-names = "sierra_reset" 258 reset-names = "sierra_reset";
256 clocks = <&wiz0_cmn_refclk_d 259 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
257 clock-names = "cmn_refclk_di 260 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
258 }; 261 };
259 }; 262 };
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