1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorpo 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy- 5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: TI J721E WIZ (SERDES Wrapper) 8 title: TI J721E WIZ (SERDES Wrapper)
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 enum: 15 enum:
16 - ti,j721e-wiz-16g 16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g 17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g 18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g 19 - ti,am64-wiz-10g
20 - ti,j7200-wiz-10g 20 - ti,j7200-wiz-10g
21 - ti,j784s4-wiz-10g 21 - ti,j784s4-wiz-10g
22 22
23 power-domains: 23 power-domains:
24 maxItems: 1 24 maxItems: 1
25 25
26 clocks: 26 clocks:
27 minItems: 3 27 minItems: 3
28 maxItems: 4 28 maxItems: 4
29 description: clock-specifier to represent 29 description: clock-specifier to represent input to the WIZ
30 30
31 clock-names: 31 clock-names:
32 minItems: 3 32 minItems: 3
33 items: 33 items:
34 - const: fck 34 - const: fck
35 - const: core_ref_clk 35 - const: core_ref_clk
36 - const: ext_ref_clk 36 - const: ext_ref_clk
37 - const: core_ref1_clk 37 - const: core_ref1_clk
38 38
39 num-lanes: 39 num-lanes:
40 minimum: 1 40 minimum: 1
41 maximum: 4 41 maximum: 4
42 42
43 "#address-cells": 43 "#address-cells":
44 const: 1 44 const: 1
45 45
46 "#size-cells": 46 "#size-cells":
47 const: 1 47 const: 1
48 48
49 "#reset-cells": 49 "#reset-cells":
50 const: 1 50 const: 1
51 51
52 "#clock-cells": 52 "#clock-cells":
53 const: 1 53 const: 1
54 54
55 ranges: true 55 ranges: true
56 56
57 typec-dir-gpios: 57 typec-dir-gpios:
58 maxItems: 1 58 maxItems: 1
59 description: 59 description:
60 GPIO to signal Type-C cable orientation 60 GPIO to signal Type-C cable orientation for lane swap.
61 If GPIO is active, lane 0 and lane 1 of 61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
62 achieve the functionality of an external !! 62 achieve the funtionality of an external type-C plug flip mux.
63 63
64 typec-dir-debounce-ms: 64 typec-dir-debounce-ms:
65 minimum: 100 65 minimum: 100
66 maximum: 1000 66 maximum: 1000
67 default: 100 67 default: 100
68 description: 68 description:
69 Number of milliseconds to wait before sa 69 Number of milliseconds to wait before sampling typec-dir-gpio.
70 If not specified, the default debounce o 70 If not specified, the default debounce of 100ms will be used.
71 Type-C spec states minimum CC pin deboun 71 Type-C spec states minimum CC pin debounce of 100 ms and maximum
72 of 200 ms. However, some solutions might 72 of 200 ms. However, some solutions might need more than 200 ms.
73 73
74 refclk-dig: 74 refclk-dig:
75 type: object 75 type: object
76 additionalProperties: false 76 additionalProperties: false
77 description: | 77 description: |
78 WIZ node should have subnode for refclk_ 78 WIZ node should have subnode for refclk_dig to select the reference
79 clock source for the reference clock use 79 clock source for the reference clock used in the PHY and PMA digital
80 logic. 80 logic.
81 deprecated: true 81 deprecated: true
82 properties: 82 properties:
83 clocks: 83 clocks:
84 minItems: 2 84 minItems: 2
85 maxItems: 4 85 maxItems: 4
86 description: Phandle to two (Torrent) 86 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
87 the inputs to refclk_dig 87 the inputs to refclk_dig
88 88
89 "#clock-cells": 89 "#clock-cells":
90 const: 0 90 const: 0
91 91
92 clock-output-names: 92 clock-output-names:
93 maxItems: 1 93 maxItems: 1
94 94
95 assigned-clocks: 95 assigned-clocks:
96 maxItems: 1 96 maxItems: 1
97 97
98 assigned-clock-parents: 98 assigned-clock-parents:
99 maxItems: 1 99 maxItems: 1
100 100
101 required: 101 required:
102 - clocks 102 - clocks
103 - "#clock-cells" 103 - "#clock-cells"
104 - assigned-clocks 104 - assigned-clocks
105 - assigned-clock-parents 105 - assigned-clock-parents
106 106
107 ti,scm: 107 ti,scm:
108 $ref: /schemas/types.yaml#/definitions/pha 108 $ref: /schemas/types.yaml#/definitions/phandle
109 description: | 109 description: |
110 phandle to System Control Module for sys 110 phandle to System Control Module for syscon regmap access.
111 111
112 patternProperties: 112 patternProperties:
113 "^pll[0|1]-refclk$": 113 "^pll[0|1]-refclk$":
114 type: object 114 type: object
115 additionalProperties: false 115 additionalProperties: false
116 description: | 116 description: |
117 WIZ node should have subnodes for each o 117 WIZ node should have subnodes for each of the PLLs present in
118 the SERDES. 118 the SERDES.
119 deprecated: true 119 deprecated: true
120 properties: 120 properties:
121 clocks: 121 clocks:
122 maxItems: 2 122 maxItems: 2
123 description: Phandle to clock nodes re 123 description: Phandle to clock nodes representing the two inputs to PLL.
124 124
125 "#clock-cells": 125 "#clock-cells":
126 const: 0 126 const: 0
127 127
128 clock-output-names: 128 clock-output-names:
129 maxItems: 1 129 maxItems: 1
130 130
131 assigned-clocks: 131 assigned-clocks:
132 maxItems: 1 132 maxItems: 1
133 133
134 assigned-clock-parents: 134 assigned-clock-parents:
135 maxItems: 1 135 maxItems: 1
136 136
137 required: 137 required:
138 - clocks 138 - clocks
139 - "#clock-cells" 139 - "#clock-cells"
140 - assigned-clocks 140 - assigned-clocks
141 - assigned-clock-parents 141 - assigned-clock-parents
142 142
143 "^cmn-refclk1?-dig-div$": 143 "^cmn-refclk1?-dig-div$":
144 type: object 144 type: object
145 additionalProperties: false 145 additionalProperties: false
146 description: 146 description:
147 WIZ node should have subnodes for each o 147 WIZ node should have subnodes for each of the PMA common refclock
148 provided by the SERDES. 148 provided by the SERDES.
149 deprecated: true 149 deprecated: true
150 properties: 150 properties:
151 clocks: 151 clocks:
152 maxItems: 1 152 maxItems: 1
153 description: Phandle to the clock node 153 description: Phandle to the clock node representing the input to the
154 divider clock. 154 divider clock.
155 155
156 "#clock-cells": 156 "#clock-cells":
157 const: 0 157 const: 0
158 158
159 clock-output-names: 159 clock-output-names:
160 maxItems: 1 160 maxItems: 1
161 161
162 required: 162 required:
163 - clocks 163 - clocks
164 - "#clock-cells" 164 - "#clock-cells"
165 165
166 "^serdes@[0-9a-f]+$": 166 "^serdes@[0-9a-f]+$":
167 type: object 167 type: object
168 description: | 168 description: |
169 WIZ node should have '1' subnode for the 169 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra 170 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
171 bindings specified in 171 bindings specified in
172 Documentation/devicetree/bindings/phy/ph 172 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
173 Torrent SERDES should follow the binding 173 Torrent SERDES should follow the bindings specified in
174 Documentation/devicetree/bindings/phy/ph 174 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
175 175
176 required: 176 required:
177 - compatible 177 - compatible
178 - power-domains 178 - power-domains
179 - clocks 179 - clocks
180 - clock-names 180 - clock-names
181 - num-lanes 181 - num-lanes
182 - "#address-cells" 182 - "#address-cells"
183 - "#size-cells" 183 - "#size-cells"
184 - "#reset-cells" 184 - "#reset-cells"
185 - ranges 185 - ranges
186 186
187 allOf: 187 allOf:
188 - if: 188 - if:
189 properties: 189 properties:
190 compatible: 190 compatible:
191 contains: 191 contains:
192 const: ti,j7200-wiz-10g 192 const: ti,j7200-wiz-10g
193 then: 193 then:
194 required: 194 required:
195 - ti,scm 195 - ti,scm
196 196
197 additionalProperties: false 197 additionalProperties: false
198 198
199 examples: 199 examples:
200 - | 200 - |
201 #include <dt-bindings/soc/ti,sci_pm_domain 201 #include <dt-bindings/soc/ti,sci_pm_domain.h>
202 202
203 wiz@5000000 { 203 wiz@5000000 {
204 compatible = "ti,j721e-wiz-16g"; 204 compatible = "ti,j721e-wiz-16g";
205 #address-cells = <1>; 205 #address-cells = <1>;
206 #size-cells = <1>; 206 #size-cells = <1>;
207 power-domains = <&k3_pds 292 TI_SCI 207 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
208 clocks = <&k3_clks 292 5>, <&k3_clk 208 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
209 clock-names = "fck", "core_ref_clk" 209 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
210 assigned-clocks = <&k3_clks 292 11> 210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 211 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
212 num-lanes = <2>; 212 num-lanes = <2>;
213 #reset-cells = <1>; 213 #reset-cells = <1>;
214 ranges = <0x5000000 0x5000000 0x100 214 ranges = <0x5000000 0x5000000 0x10000>;
215 215
216 pll0-refclk { 216 pll0-refclk {
217 clocks = <&k3_clks 293 13>, 217 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
218 #clock-cells = <0>; 218 #clock-cells = <0>;
219 assigned-clocks = <&wiz1_pll 219 assigned-clocks = <&wiz1_pll0_refclk>;
220 assigned-clock-parents = <&k 220 assigned-clock-parents = <&k3_clks 293 13>;
221 }; 221 };
222 222
223 pll1-refclk { 223 pll1-refclk {
224 clocks = <&k3_clks 293 0>, < 224 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
225 #clock-cells = <0>; 225 #clock-cells = <0>;
226 assigned-clocks = <&wiz1_pll 226 assigned-clocks = <&wiz1_pll1_refclk>;
227 assigned-clock-parents = <&k 227 assigned-clock-parents = <&k3_clks 293 0>;
228 }; 228 };
229 229
230 cmn-refclk-dig-div { 230 cmn-refclk-dig-div {
231 clocks = <&wiz1_refclk_dig>; 231 clocks = <&wiz1_refclk_dig>;
232 #clock-cells = <0>; 232 #clock-cells = <0>;
233 }; 233 };
234 234
235 cmn-refclk1-dig-div { 235 cmn-refclk1-dig-div {
236 clocks = <&wiz1_pll1_refclk> 236 clocks = <&wiz1_pll1_refclk>;
237 #clock-cells = <0>; 237 #clock-cells = <0>;
238 }; 238 };
239 239
240 refclk-dig { 240 refclk-dig {
241 clocks = <&k3_clks 292 11>, 241 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
242 <&dummy_cmn_refclk>, 242 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
243 #clock-cells = <0>; 243 #clock-cells = <0>;
244 assigned-clocks = <&wiz0_ref 244 assigned-clocks = <&wiz0_refclk_dig>;
245 assigned-clock-parents = <&k 245 assigned-clock-parents = <&k3_clks 292 11>;
246 }; 246 };
247 247
248 serdes@5000000 { 248 serdes@5000000 {
249 compatible = "ti,sierra-phy- 249 compatible = "ti,sierra-phy-t0";
250 reg-names = "serdes"; 250 reg-names = "serdes";
251 reg = <0x5000000 0x10000>; 251 reg = <0x5000000 0x10000>;
252 #address-cells = <1>; 252 #address-cells = <1>;
253 #size-cells = <0>; 253 #size-cells = <0>;
254 resets = <&serdes_wiz0 0>; 254 resets = <&serdes_wiz0 0>;
255 reset-names = "sierra_reset" 255 reset-names = "sierra_reset";
256 clocks = <&wiz0_cmn_refclk_d 256 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
257 clock-names = "cmn_refclk_di 257 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
258 }; 258 };
259 }; 259 };
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