1 Actions Semi S900 Pin Controller
2
3 This binding describes the pin controller foun
4
5 Required Properties:
6
7 - compatible: Should be "actions,s900-pinctr
8 - reg: Should contain the register ba
9 the pin controller.
10 - clocks: phandle of the clock feeding t
11 - gpio-controller: Marks the device node as a
12 - gpio-ranges: Specifies the mapping between g
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell i
15 and the second cell is used for
16 - interrupt-controller: Marks the device node
17 - #interrupt-cells: Specifies the number of ce
18 interrupt. Shall be set t
19 defines the interrupt numb
20 the trigger flags describe
21 bindings/interrupt-control
22 - interrupts: The interrupt outputs from the c
23 interrupt per GPIO bank. The num
24 on the number of GPIO banks on t
25 ordered by bank, starting with b
26
27 Please refer to pinctrl-bindings.txt in this d
28 common pinctrl bindings used by client devices
29 phrase "pin configuration node".
30
31 The pin configuration nodes act as a container
32 subnodes. Each of these subnodes represents so
33 pin, a group, or a list of pins or groups. Thi
34 mux function to select on those group(s), and
35 parameters, such as pull-up, drive strength, e
36
37 PIN CONFIGURATION NODES:
38
39 The name of each subnode is not important; all
40 and processed purely based on their content.
41
42 Each subnode only affects those parameters tha
43 other words, a subnode that lists a mux functi
44 parameters implies no information about any pi
45 Similarly, a pin subnode that describes a pull
46 information about e.g. the mux function.
47
48 Pinmux functions are available only for the pi
49 parameters are available for both pin groups a
50
51 The following generic properties as defined in
52 to specify in a pin configuration subnode:
53
54 Required Properties:
55
56 - pins: An array of strings, each st
57 These pins are used for sele
58 trigger parameters. The foll
59 available:
60
61 eth_txd0, eth_txd1, eth_txen
62 eth_rxd1, eth_rxd0, eth_ref_
63 sirq0, sirq1, sirq2, i2s_d0,
64 i2s_mclk0, i2s_d1, i2s_bclk1
65 pcm1_in, pcm1_clk, pcm1_sync
66 eram_a6, eram_a7, eram_a8, e
67 lvds_oep, lvds_oen, lvds_odp
68 lvds_ocn, lvds_obp, lvds_obn
69 lvds_eep, lvds_een, lvds_edp
70 lvds_ecn, lvds_ebp, lvds_ebn
71 sd0_d0, sd0_d1, sd0_d2, sd0_
72 sd1_d2, sd1_d3, sd0_cmd, sd0
73 spi0_sclk, spi0_ss, spi0_mis
74 uart0_tx, uart2_rx, uart2_tx
75 uart3_rx, uart3_tx, uart3_rt
76 uart4_tx, i2c0_sclk, i2c0_sd
77 i2c2_sclk, i2c2_sdata, csi0_
78 csi0_dp1, csi0_cn, csi0_cp,
79 csi0_dp3, dsi_dp3, dsi_dn3,
80 dsi_cn, dsi_dp0, dsi_dn0, ds
81 csi1_dn0,csi1_dp0,csi1_dn1,
82 sensor0_ckout, nand0_d0, nan
83 nand0_d4, nand0_d5, nand0_d6
84 nand0_dqsn, nand0_ale, nand0
85 nand0_ceb2, nand0_ceb3, nand
86 nand1_d3, nand1_d4, nand1_d5
87 nand1_dqsn, nand1_ale, nand1
88 nand1_ceb2, nand1_ceb3, sgpi
89
90 - groups: An array of strings, each st
91 group. These pin groups are
92 functions.
93
94 lvds_oxx_uart4_mfp, rmii_mdc
95 sirq1_mfp, rmii_txd0_mfp, rm
96 rmii_rxer_mfp, rmii_crs_dv_m
97 rmii_ref_clk_mfp, i2s_d0_mfp
98 i2s_bclk0_mfp, i2s_bclk1_mcl
99 pcm1_clk_mfp, pcm1_sync_mfp,
100 eram_a7_mfp, eram_a8_mfp, er
101 eram_a11_mfp, lvds_oep_odn_m
102 lvds_oap_oan_mfp, lvds_e_mfp
103 spi0_miso_mfp, uart2_rtsb_mf
104 uart3_ctsb_mfp, sd0_d0_mfp,
105 sd1_d0_d3_mfp, sd0_cmd_mfp,
106 uart0_rx_mfp, nand0_d0_ceb3_
107 csi0_cn_cp_mfp, csi0_dn0_dp3
108 dsi_dp3_dn1_mfp, dsi_cp_dn0_
109 nand1_d0_ceb1_mfp, nand1_ceb
110 csi1_dn0_dp0_mfp, uart4_rx_t
111
112
113 These pin groups are used fo
114 parameters.
115
116 sgpio3_drv, sgpio2_drv, sgpi
117 rmii_tx_d0_d1_drv, rmii_txen
118 rmii_rx_d1_d0_drv, rmii_ref_
119 sirq_0_1_drv, sirq2_drv, i2s
120 i2s_blk1_mclk1_drv, pcm1_in_
121 lvds_oep_odn_drv, lvds_ocp_o
122 sd1_d3_d0_drv, sd0_sd1_cmd_c
123 spi0_ss_miso_drv, uart0_rx_t
124 uart3_drv, i2c0_drv, i2c1_dr
125
126 These pin groups are used fo
127 parameters.
128
129 sgpio3_sr, sgpio2_sr, sgpio1
130 rmii_txen_rxer_sr, rmii_crs_
131 rmii_ref_clk_sr, rmii_mdc_md
132 i2s_do_d1_sr, i2s_lr_m_clk0_
133 pcm1_in_out_sr, sd1_d3_d0_sr
134 spi0_sclk_mosi_sr, spi0_ss_m
135 uart4_rx_tx_sr, uart2_sr, ua
136 sensor0_sr
137
138 - function: An array of strings, each st
139 pinmux functions. These func
140 the corresponding pin groups
141 pinmux functions available:
142
143 eram, eth_rmii, eth_smii, sp
144 uart0, uart1, uart2, uart3,
145 pcm0, pcm1, jtag, pwm0, pwm1
146 sd1, sd2, sd3, i2c0, i2c1, i
147 usb30, usb20, gpu, mipi_csi0
148 nand1, spdif, sirq0, sirq1,
149
150 Optional Properties:
151
152 - bias-bus-hold: No arguments. The specified
153 state value.
154 - bias-high-impedance: No arguments. The speci
155 as high impedance.
156 - bias-pull-down: No arguments. The specified
157 pull down.
158 - bias-pull-up: No arguments. The specified
159 pull up.
160 - input-schmitt-enable: No arguments: Enable s
161 pins
162 - input-schmitt-disable: No arguments: Disable
163 pins
164 - slew-rate: Integer. Sets slew rate for
165 Valid values are:
166 <0> - Slow
167 <1> - Fast
168 - drive-strength: Integer. Selects the drive s
169 pins in mA.
170 Valid values are:
171 <2>
172 <4>
173 <8>
174 <12>
175
176 Example:
177
178 pinctrl: pinctrl@e01b0000 {
179 compatible = "actions,s900-p
180 reg = <0x0 0xe01b0000 0x0 0x
181 clocks = <&cmu CLK_GPIO>;
182 gpio-controller;
183 gpio-ranges = <&pinctrl 0 0
184 #gpio-cells = <2>;
185 interrupt-controller;
186 #interrupt-cells = <2>;
187 interrupts = <GIC_SPI 36 IRQ
188 <GIC_SPI 37 IRQ
189 <GIC_SPI 38 IRQ
190 <GIC_SPI 39 IRQ
191 <GIC_SPI 40 IRQ
192 <GIC_SPI 16 IRQ
193
194 uart2-default: uart2-default
195 pinmux {
196 groups = "lv
197 function = "
198 };
199 pinconf {
200 groups = "lv
201 drive-streng
202 };
203 };
204 };
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