1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atm 4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Microchip PIO3 Pinmux Controller 7 title: Microchip PIO3 Pinmux Controller
8 8
9 maintainers: 9 maintainers:
10 - Manikandan Muralidharan <manikandan.m@micro 10 - Manikandan Muralidharan <manikandan.m@microchip.com>
11 11
12 description: 12 description:
13 The AT91 Pinmux Controller, enables the IC t 13 The AT91 Pinmux Controller, enables the IC to share one PAD to several
14 functional blocks. The sharing is done by mu 14 functional blocks. The sharing is done by multiplexing the PAD input/output
15 signals. For each PAD there are up to 8 muxi 15 signals. For each PAD there are up to 8 muxing options (called periph modes).
16 Since different modules require different PA 16 Since different modules require different PAD settings (like pull up, keeper,
17 etc) the controller controls also the PAD se 17 etc) the controller controls also the PAD settings parameters.
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 oneOf: 21 oneOf:
22 - items: 22 - items:
23 - enum: 23 - enum:
24 - atmel,at91rm9200-pinctrl 24 - atmel,at91rm9200-pinctrl
25 - atmel,at91sam9x5-pinctrl 25 - atmel,at91sam9x5-pinctrl
26 - atmel,sama5d3-pinctrl 26 - atmel,sama5d3-pinctrl
27 - microchip,sam9x60-pinctrl 27 - microchip,sam9x60-pinctrl
28 - const: simple-mfd 28 - const: simple-mfd
29 - items: 29 - items:
30 - enum: 30 - enum:
31 - microchip,sam9x7-pinctrl 31 - microchip,sam9x7-pinctrl
32 - const: microchip,sam9x60-pinctrl 32 - const: microchip,sam9x60-pinctrl
33 - const: simple-mfd 33 - const: simple-mfd
34 34
35 '#address-cells': 35 '#address-cells':
36 const: 1 36 const: 1
37 37
38 '#size-cells': 38 '#size-cells':
39 const: 1 39 const: 1
40 40
41 ranges: true 41 ranges: true
42 42
43 atmel,mux-mask: 43 atmel,mux-mask:
44 $ref: /schemas/types.yaml#/definitions/uin 44 $ref: /schemas/types.yaml#/definitions/uint32-matrix
45 description: | 45 description: |
46 Array of mask (periph per bank) to descr 46 Array of mask (periph per bank) to describe if a pin can be
47 configured in this periph mode. All the 47 configured in this periph mode. All the periph and bank need to
48 be described. 48 be described.
49 49
50 #How to create such array: 50 #How to create such array:
51 51
52 Each column will represent the possible 52 Each column will represent the possible peripheral of the pinctrl
53 Each line will represent a pio bank 53 Each line will represent a pio bank
54 54
55 #Example: 55 #Example:
56 56
57 In at91sam9260.dtsi, 57 In at91sam9260.dtsi,
58 Peripheral: 2 ( A and B) 58 Peripheral: 2 ( A and B)
59 Bank: 3 (A, B and C) 59 Bank: 3 (A, B and C)
60 60
61 # A B 61 # A B
62 0xffffffff 0xffc00c3b # pioA 62 0xffffffff 0xffc00c3b # pioA
63 0xffffffff 0x7fff3ccf # pioB 63 0xffffffff 0x7fff3ccf # pioB
64 0xffffffff 0x007fffff # pioC 64 0xffffffff 0x007fffff # pioC
65 65
66 For each peripheral/bank we will describ 66 For each peripheral/bank we will describe in a u32 if a pin can be
67 configured in it by putting 1 to the pin 67 configured in it by putting 1 to the pin bit (1 << pin)
68 68
69 Let's take the pioA on peripheral B whos 69 Let's take the pioA on peripheral B whose value is 0xffc00c3b
70 From the datasheet Table 10-2. 70 From the datasheet Table 10-2.
71 Peripheral B 71 Peripheral B
72 PA0 MCDB0 72 PA0 MCDB0
73 PA1 MCCDB 73 PA1 MCCDB
74 PA2 74 PA2
75 PA3 MCDB3 75 PA3 MCDB3
76 PA4 MCDB2 76 PA4 MCDB2
77 PA5 MCDB1 77 PA5 MCDB1
78 PA6 78 PA6
79 PA7 79 PA7
80 PA8 80 PA8
81 PA9 81 PA9
82 PA10 ETX2 82 PA10 ETX2
83 PA11 ETX3 83 PA11 ETX3
84 PA12 84 PA12
85 PA13 85 PA13
86 PA14 86 PA14
87 PA15 87 PA15
88 PA16 88 PA16
89 PA17 89 PA17
90 PA18 90 PA18
91 PA19 91 PA19
92 PA20 92 PA20
93 PA21 93 PA21
94 PA22 ETXER 94 PA22 ETXER
95 PA23 ETX2 95 PA23 ETX2
96 PA24 ETX3 96 PA24 ETX3
97 PA25 ERX2 97 PA25 ERX2
98 PA26 ERX3 98 PA26 ERX3
99 PA27 ERXCK 99 PA27 ERXCK
100 PA28 ECRS 100 PA28 ECRS
101 PA29 ECOL 101 PA29 ECOL
102 PA30 RXD4 102 PA30 RXD4
103 PA31 TXD4 103 PA31 TXD4
104 104
105 allOf: 105 allOf:
106 - $ref: pinctrl.yaml# 106 - $ref: pinctrl.yaml#
107 107
108 required: 108 required:
109 - compatible 109 - compatible
110 - ranges 110 - ranges
111 - "#address-cells" 111 - "#address-cells"
112 - "#size-cells" 112 - "#size-cells"
113 - atmel,mux-mask 113 - atmel,mux-mask
114 114
115 patternProperties: 115 patternProperties:
116 'gpio@[0-9a-f]+$': 116 'gpio@[0-9a-f]+$':
117 $ref: /schemas/gpio/atmel,at91rm9200-gpio. 117 $ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml
118 unevaluatedProperties: false 118 unevaluatedProperties: false
119 119
120 additionalProperties: 120 additionalProperties:
121 type: object 121 type: object
122 additionalProperties: 122 additionalProperties:
123 type: object 123 type: object
124 additionalProperties: false 124 additionalProperties: false
125 125
126 properties: 126 properties:
127 atmel,pins: 127 atmel,pins:
128 $ref: /schemas/types.yaml#/definitions 128 $ref: /schemas/types.yaml#/definitions/uint32-matrix
129 description: | 129 description: |
130 Each entry consists of 4 integers an 130 Each entry consists of 4 integers and represents the pins
131 mux and config setting.The format is 131 mux and config setting.The format is
132 atmel,pins = <PIN_BANK PIN_BANK_NUM 132 atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
133 Supported pin number and mux varies 133 Supported pin number and mux varies for different SoCs, and
134 are defined in <include/dt-bindings/ 134 are defined in <include/dt-bindings/pinctrl/at91.h>.
135 items: 135 items:
136 items: 136 items:
137 - description: 137 - description:
138 Pin bank 138 Pin bank
139 - description: 139 - description:
140 Pin bank index 140 Pin bank index
141 - description: 141 - description:
142 Peripheral function 142 Peripheral function
143 - description: 143 - description:
144 Pad configuration 144 Pad configuration
145 145
146 examples: 146 examples:
147 - | 147 - |
148 #include <dt-bindings/clock/at91.h> 148 #include <dt-bindings/clock/at91.h>
149 #include <dt-bindings/interrupt-controlle 149 #include <dt-bindings/interrupt-controller/irq.h>
150 #include <dt-bindings/pinctrl/at91.h> 150 #include <dt-bindings/pinctrl/at91.h>
151 151
152 pinctrl@fffff400 { 152 pinctrl@fffff400 {
153 #address-cells = <1>; 153 #address-cells = <1>;
154 #size-cells = <1>; 154 #size-cells = <1>;
155 compatible = "atmel,at91rm9200-pinctrl" 155 compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
156 ranges = <0xfffff400 0xfffff400 0x600>; 156 ranges = <0xfffff400 0xfffff400 0x600>;
157 157
158 atmel,mux-mask = < 158 atmel,mux-mask = <
159 /* A B */ 159 /* A B */
160 0xffffffff 0xffc00c3b /* pioA */ 160 0xffffffff 0xffc00c3b /* pioA */
161 0xffffffff 0x7fff3ccf /* pioB */ 161 0xffffffff 0x7fff3ccf /* pioB */
162 0xffffffff 0x007fffff /* pioC */ 162 0xffffffff 0x007fffff /* pioC */
163 >; 163 >;
164 164
165 dbgu { 165 dbgu {
166 pinctrl_dbgu: dbgu-0 { 166 pinctrl_dbgu: dbgu-0 {
167 atmel,pins = 167 atmel,pins =
168 <AT91_PIOB 14 AT91_PERIPH_A AT91_ 168 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
169 AT91_PIOB 15 AT91_PERIPH_A AT91_ 169 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
170 }; 170 };
171 }; 171 };
172 172
173 pioA: gpio@fffff400 { 173 pioA: gpio@fffff400 {
174 compatible = "atmel,at91rm9200-gpio"; 174 compatible = "atmel,at91rm9200-gpio";
175 reg = <0xfffff400 0x200>; 175 reg = <0xfffff400 0x200>;
176 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1 176 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
177 #gpio-cells = <2>; 177 #gpio-cells = <2>;
178 gpio-controller; 178 gpio-controller;
179 interrupt-controller; 179 interrupt-controller;
180 #interrupt-cells = <2>; 180 #interrupt-cells = <2>;
181 clocks = <&pmc PMC_TYPE_PERIPHERAL 2> 181 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
182 }; 182 };
183 }; 183 };
184 ... 184 ...
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