1 Axis ARTPEC-6 Pin Controller 1 Axis ARTPEC-6 Pin Controller
2 2
3 Required properties: 3 Required properties:
4 - compatible: "axis,artpec6-pinctrl". 4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical ad 5 - reg: Should contain the register physical address and length for the pin
6 controller. 6 controller.
7 7
8 A pinctrl node should contain at least one sub 8 A pinctrl node should contain at least one subnode representing the pinctrl
9 groups available on the machine. Each subnode 9 groups available on the machine. Each subnode will list the mux function
10 required and what pin group it will use. Each 10 required and what pin group it will use. Each subnode will also configure the
11 drive strength and bias pullup of the pin grou 11 drive strength and bias pullup of the pin group. If either of these options is
12 not set, its actual value will be unspecified. 12 not set, its actual value will be unspecified.
13 13
14 14
15 Required subnode-properties: 15 Required subnode-properties:
16 - function: Function to mux. 16 - function: Function to mux.
17 - groups: Name of the pin group to use for the 17 - groups: Name of the pin group to use for the function above.
18 18
19 Available functions and groups (functi 19 Available functions and groups (function: group0, group1...):
20 gpio: cpuclkoutgrp0, udlclkout 20 gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
21 i2c3grp0, i2s0grp0, i2s1 21 i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
22 spi1grp0, pciedebuggrp0, !! 22 spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
23 uart1grp0, uart1grp1, ua !! 23 uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0,
24 uart3grp0, uart4grp0, ua <<
25 uart5nocts 24 uart5nocts
26 cpuclkout: cpuclkoutgrp0 25 cpuclkout: cpuclkoutgrp0
27 udlclkout: udlclkoutgrp0 26 udlclkout: udlclkoutgrp0
28 i2c1: i2c1grp0 27 i2c1: i2c1grp0
29 i2c2: i2c2grp0 28 i2c2: i2c2grp0
30 i2c3: i2c3grp0 29 i2c3: i2c3grp0
31 i2s0: i2s0grp0 30 i2s0: i2s0grp0
32 i2s1: i2s1grp0 31 i2s1: i2s1grp0
33 i2srefclk: i2srefclkgrp0 32 i2srefclk: i2srefclkgrp0
34 spi0: spi0grp0 33 spi0: spi0grp0
35 spi1: spi1grp0 34 spi1: spi1grp0
36 pciedebug: pciedebuggrp0 35 pciedebug: pciedebuggrp0
37 uart0: uart0grp0, uart0grp1, u !! 36 uart0: uart0grp0, uart0grp1
38 uart1: uart1grp0, uart1grp1 !! 37 uart1: uart1grp0
39 uart2: uart2grp0, uart2grp1, u !! 38 uart2: uart2grp0, uart2grp1
40 uart3: uart3grp0 39 uart3: uart3grp0
41 uart4: uart4grp0, uart4grp1 !! 40 uart4: uart4grp0
42 uart5: uart5grp0, uart5grp1, u !! 41 uart5: uart5grp0, uart5nocts
43 nand: nandgrp0 42 nand: nandgrp0
44 sdio0: sdio0grp0 43 sdio0: sdio0grp0
45 sdio1: sdio1grp0 44 sdio1: sdio1grp0
46 ethernet: ethernetgrp0 45 ethernet: ethernetgrp0
47 46
48 47
49 Optional subnode-properties (see pinctrl-bindi 48 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and N 49 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up 50 - bias-pull-up
52 - bias-disable 51 - bias-disable
53 52
54 Examples: 53 Examples:
55 pinctrl@f801d000 { 54 pinctrl@f801d000 {
56 compatible = "axis,artpec6-pinctrl"; 55 compatible = "axis,artpec6-pinctrl";
57 reg = <0xf801d000 0x400>; 56 reg = <0xf801d000 0x400>;
58 57
59 pinctrl_uart0: uart0grp { 58 pinctrl_uart0: uart0grp {
60 function = "uart0"; 59 function = "uart0";
61 groups = "uart0grp0"; 60 groups = "uart0grp0";
62 drive-strength = <4>; 61 drive-strength = <4>;
63 bias-pull-up; 62 bias-pull-up;
64 }; 63 };
65 pinctrl_uart3: uart3grp { 64 pinctrl_uart3: uart3grp {
66 function = "uart3"; 65 function = "uart3";
67 groups = "uart3grp0"; 66 groups = "uart3grp0";
68 }; 67 };
69 }; 68 };
70 uart0: uart@f8036000 { 69 uart0: uart@f8036000 {
71 compatible = "arm,pl011", "arm,primece 70 compatible = "arm,pl011", "arm,primecell";
72 reg = <0xf8036000 0x1000>; 71 reg = <0xf8036000 0x1000>;
73 interrupts = <0 104 IRQ_TYPE_LEVEL_HIG 72 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&pll2div24>, <&apb_pclk>; 73 clocks = <&pll2div24>, <&apb_pclk>;
75 clock-names = "uart_clk", "apb_pclk"; 74 clock-names = "uart_clk", "apb_pclk";
76 pinctrl-names = "default"; 75 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_uart0>; 76 pinctrl-0 = <&pinctrl_uart0>;
78 }; 77 };
79 uart3: uart@f8039000 { 78 uart3: uart@f8039000 {
80 compatible = "arm,pl011", "arm,primece 79 compatible = "arm,pl011", "arm,primecell";
81 reg = <0xf8039000 0x1000>; 80 reg = <0xf8039000 0x1000>;
82 interrupts = <0 128 IRQ_TYPE_LEVEL_HIG 81 interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&pll2div24>, <&apb_pclk>; 82 clocks = <&pll2div24>, <&apb_pclk>;
84 clock-names = "uart_clk", "apb_pclk"; 83 clock-names = "uart_clk", "apb_pclk";
85 pinctrl-names = "default"; 84 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_uart3>; 85 pinctrl-0 = <&pinctrl_uart3>;
87 }; 86 };
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