1 * Freescale IOMUX Controller (IOMUXC) for i.MX
2
3 The IOMUX Controller (IOMUXC), together with t
4 to share one PAD to several functional blocks.
5 multiplexing the PAD input/output signals. For
6 8 muxing options (called ALT modes). Since dif
7 different PAD settings (like pull up, keeper,
8 also the PAD settings parameters.
9
10 Please refer to pinctrl-bindings.txt in this d
11 common pinctrl bindings used by client devices
12 phrase "pin configuration node".
13
14 Freescale IMX pin configuration node is a node
15 used for a specific device or function. This n
16 of the pins in that group. The 'mux' selects t
17 mode) this pin can work on and the 'config' co
18 such as pull-up, open drain, drive strength, e
19
20 Required properties for iomux controller:
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt b
23
24 Required properties for pin configuration node
25 - fsl,pins: each entry consists of 6 integers
26 setting for one pin. The first 5 integers <m
27 input_val> are specified using a PIN_FUNC_ID
28 imx*-pinfunc.h under device tree source fold
29 the pad setting value like pull-up on this p
30 looks like <PIN_FUNC_ID CONFIG> in the examp
31
32 Bits used for CONFIG:
33 NO_PAD_CTL(1 << 31): indicate this pin does no
34
35 SION(1 << 30): Software Input On Field.
36 Force the selected mux mode input path no matt
37 By default the input path is determined by fun
38 mux mode (regular).
39
40 Other bits are used for PAD setting.
41 Please refer to each fsl,<soc>-pinctrl,txt bin
42 of bits definitions.
43
44 NOTE:
45 Some requirements for using fsl,imx-pinctrl bi
46 1. We have pin function node defined under iom
47 what pinmux functions this SoC supports.
48 2. The pin configuration node intends to work
49 to be defined under that specific function
50 The function node's name should represent w
51 this group of pins in this pin configuratio
52 3. The driver can use the function node's name
53 name describe the pin function and group hi
54 For example, Linux IMX pinctrl driver takes
55 as the function name and pin configuration
56 create the map table.
57 4. Each pin configuration node should have a p
58 configurations by referring to the phandle
59
60 Examples:
61 usdhc@219c000 { /* uSDHC4 */
62 non-removable;
63 vmmc-supply = <®_3p3v>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_usdhc4_1>;
66 };
67
68 iomuxc@20e0000 {
69 compatible = "fsl,imx6q-iomuxc";
70 reg = <0x020e0000 0x4000>;
71
72 /* shared pinctrl settings */
73 usdhc4 {
74 pinctrl_usdhc4_1: usdhc4grp-1
75 fsl,pins = <
76 MX6QDL_PAD_SD4
77 MX6QDL_PAD_SD4
78 MX6QDL_PAD_SD4
79 MX6QDL_PAD_SD4
80 MX6QDL_PAD_SD4
81 MX6QDL_PAD_SD4
82 MX6QDL_PAD_SD4
83 MX6QDL_PAD_SD4
84 MX6QDL_PAD_SD4
85 MX6QDL_PAD_SD4
86 >;
87 };
88 ....
89 };
90 Refer to the IOMUXC controller chapter in imx6
91 0x17059 means enable hysteresis, 47KOhm Pull U
92 80Ohm driver strength and Fast Slew Rate.
93 User should refer to each SoC spec to set the
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