1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 %YAML 1.2 2 %YAML 1.2 3 --- 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/fsl 4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 title: Freescale IMX6UL IOMUX Controller 7 title: Freescale IMX6UL IOMUX Controller 8 8 9 maintainers: 9 maintainers: 10 - Dong Aisheng <aisheng.dong@nxp.com> 10 - Dong Aisheng <aisheng.dong@nxp.com> 11 11 12 description: 12 description: 13 Please refer to fsl,imx-pinctrl.txt and pinc 13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory 14 for common binding part and usage. 14 for common binding part and usage. 15 15 16 allOf: 16 allOf: 17 - $ref: pinctrl.yaml# 17 - $ref: pinctrl.yaml# 18 18 19 properties: 19 properties: 20 compatible: 20 compatible: 21 enum: 21 enum: 22 - fsl,imx6ul-iomuxc 22 - fsl,imx6ul-iomuxc 23 - fsl,imx6ull-iomuxc-snvs 23 - fsl,imx6ull-iomuxc-snvs 24 24 25 reg: 25 reg: 26 maxItems: 1 26 maxItems: 1 27 27 28 # Client device subnode's properties 28 # Client device subnode's properties 29 patternProperties: 29 patternProperties: 30 'grp$': 30 'grp$': 31 type: object 31 type: object 32 description: 32 description: 33 Pinctrl node's client devices use subnod 33 Pinctrl node's client devices use subnodes for desired pin configuration. 34 Client device subnodes use below standar 34 Client device subnodes use below standard properties. 35 35 36 properties: 36 properties: 37 fsl,pins: 37 fsl,pins: 38 description: 38 description: 39 each entry consists of 6 integers an 39 each entry consists of 6 integers and represents the mux and config 40 setting for one pin. The first 5 int 40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg 41 mux_val input_val> are specified usi 41 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can 42 be found in <arch/arm/boot/dts/imx6u 42 be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer 43 CONFIG is the pad setting value like 43 CONFIG is the pad setting value like pull-up on this pin. Please 44 refer to i.MX6UL Reference Manual fo 44 refer to i.MX6UL Reference Manual for detailed CONFIG settings. 45 $ref: /schemas/types.yaml#/definitions 45 $ref: /schemas/types.yaml#/definitions/uint32-matrix 46 items: 46 items: 47 items: 47 items: 48 - description: | 48 - description: | 49 "mux_reg" indicates the offset 49 "mux_reg" indicates the offset of mux register. 50 - description: | 50 - description: | 51 "conf_reg" indicates the offse 51 "conf_reg" indicates the offset of pad configuration register. 52 - description: | 52 - description: | 53 "input_reg" indicates the offs 53 "input_reg" indicates the offset of select input register. 54 - description: | 54 - description: | 55 "mux_val" indicates the mux va 55 "mux_val" indicates the mux value to be applied. 56 - description: | 56 - description: | 57 "input_val" indicates the sele 57 "input_val" indicates the select input value to be applied. 58 - description: | 58 - description: | 59 "pad_setting" indicates the pa 59 "pad_setting" indicates the pad configuration value to be applied: 60 PAD_CTL_HYS 60 PAD_CTL_HYS (1 << 16) 61 PAD_CTL_PUS_100K_DOWN 61 PAD_CTL_PUS_100K_DOWN (0 << 14) 62 PAD_CTL_PUS_47K_UP 62 PAD_CTL_PUS_47K_UP (1 << 14) 63 PAD_CTL_PUS_100K_UP 63 PAD_CTL_PUS_100K_UP (2 << 14) 64 PAD_CTL_PUS_22K_UP 64 PAD_CTL_PUS_22K_UP (3 << 14) 65 PAD_CTL_PUE 65 PAD_CTL_PUE (1 << 13) 66 PAD_CTL_PKE 66 PAD_CTL_PKE (1 << 12) 67 PAD_CTL_ODE 67 PAD_CTL_ODE (1 << 11) 68 PAD_CTL_SPEED_LOW 68 PAD_CTL_SPEED_LOW (0 << 6) 69 PAD_CTL_SPEED_MED 69 PAD_CTL_SPEED_MED (1 << 6) 70 PAD_CTL_SPEED_HIGH 70 PAD_CTL_SPEED_HIGH (3 << 6) 71 PAD_CTL_DSE_DISABLE 71 PAD_CTL_DSE_DISABLE (0 << 3) 72 PAD_CTL_DSE_260ohm 72 PAD_CTL_DSE_260ohm (1 << 3) 73 PAD_CTL_DSE_130ohm 73 PAD_CTL_DSE_130ohm (2 << 3) 74 PAD_CTL_DSE_87ohm 74 PAD_CTL_DSE_87ohm (3 << 3) 75 PAD_CTL_DSE_65ohm 75 PAD_CTL_DSE_65ohm (4 << 3) 76 PAD_CTL_DSE_52ohm 76 PAD_CTL_DSE_52ohm (5 << 3) 77 PAD_CTL_DSE_43ohm 77 PAD_CTL_DSE_43ohm (6 << 3) 78 PAD_CTL_DSE_37ohm 78 PAD_CTL_DSE_37ohm (7 << 3) 79 PAD_CTL_SRE_FAST 79 PAD_CTL_SRE_FAST (1 << 0) 80 PAD_CTL_SRE_SLOW 80 PAD_CTL_SRE_SLOW (0 << 0) 81 81 82 required: 82 required: 83 - fsl,pins 83 - fsl,pins 84 84 85 additionalProperties: false 85 additionalProperties: false 86 86 87 required: 87 required: 88 - compatible 88 - compatible 89 - reg 89 - reg 90 90 91 additionalProperties: false 91 additionalProperties: false 92 92 93 examples: 93 examples: 94 - | 94 - | 95 iomuxc: pinctrl@20e0000 { 95 iomuxc: pinctrl@20e0000 { 96 compatible = "fsl,imx6ul-iomuxc"; 96 compatible = "fsl,imx6ul-iomuxc"; 97 reg = <0x020e0000 0x4000>; 97 reg = <0x020e0000 0x4000>; 98 98 99 mux_uart: uartgrp { 99 mux_uart: uartgrp { 100 fsl,pins = < 100 fsl,pins = < 101 0x0084 0x0310 0x0000 0 0 0x1b0b1 101 0x0084 0x0310 0x0000 0 0 0x1b0b1 102 0x0088 0x0314 0x0624 0 3 0x1b0b1 102 0x0088 0x0314 0x0624 0 3 0x1b0b1 103 >; 103 >; 104 }; 104 }; 105 }; 105 }; 106 - | 106 - | 107 iomuxc_snvs: pinctrl@2290000 { 107 iomuxc_snvs: pinctrl@2290000 { 108 compatible = "fsl,imx6ull-iomuxc-snvs"; 108 compatible = "fsl,imx6ull-iomuxc-snvs"; 109 reg = <0x02290000 0x4000>; 109 reg = <0x02290000 0x4000>; 110 110 111 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 111 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 112 fsl,pins = < 112 fsl,pins = < 113 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 113 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 114 >; 114 >; 115 }; 115 }; 116 }; 116 };
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