1 * Freescale i.MX7ULP IOMUX Controller 1 * Freescale i.MX7ULP IOMUX Controller
2 2
3 i.MX 7ULP has three IOMUXC instances: IOMUXC0 3 i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
4 ports and IOMUXC DDR for DDR interface. 4 ports and IOMUXC DDR for DDR interface.
5 5
6 Note: 6 Note:
7 This binding doc is only for the IOMUXC1 suppo 7 This binding doc is only for the IOMUXC1 support in A7 Domain and it only
8 supports generic pin config. 8 supports generic pin config.
9 9
10 Please refer to fsl,imx-pinctrl.txt in this di !! 10 Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
11 part and usage. !! 11 binding.
>> 12
>> 13 === Pin Controller Node ===
12 14
13 Required properties: 15 Required properties:
14 - compatible: "fsl,imx7ulp-iomuxc1". !! 16 - compatible: "fsl,imx7ulp-iomuxc1"
15 - fsl,pins: Each entry consists of 5 integ !! 17 - reg: Should contain the base physical address and size of the iomuxc
16 and config setting for one pin !! 18 registers.
17 <mux_conf_reg input_reg mux_mo !! 19
18 using a PIN_FUNC_ID macro, whi !! 20 === Pin Configuration Node ===
19 imx7ulp-pinfunc.h in the devic !! 21 - pinmux: One integers array, represents a group of pins mux setting.
20 The last integer CONFIG is the !! 22 The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
21 pull-up on this pin. !! 23 a specific function.
22 !! 24
23 Please refer to i.MX7ULP Refer !! 25 NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
24 CONFIG settings. !! 26 and config register as follows:
25 !! 27 <mux_conf_reg input_reg mux_mode input_val>
26 CONFIG bits definition: !! 28
27 PAD_CTL_OBE (1 << 17) !! 29 Refer to imx7ulp-pinfunc.h in in device tree source folder for all
28 PAD_CTL_IBE (1 << 16) !! 30 available imx7ulp PIN_FUNC_ID.
29 PAD_CTL_LK (1 << 16) !! 31
30 PAD_CTL_DSE_HI (1 << 6) !! 32 Optional Properties:
31 PAD_CTL_DSE_STD (0 << 6) !! 33 - drive-strength Integer. Controls Drive Strength
32 PAD_CTL_ODE (1 << 5) !! 34 0: Standard
33 PAD_CTL_PUSH_PULL (0 << 5) !! 35 1: Hi Driver
34 PAD_CTL_SRE_SLOW (1 << 2) !! 36 - drive-push-pull Bool. Enable Pin Push-pull
35 PAD_CTL_SRE_STD (0 << 2) !! 37 - drive-open-drain Bool. Enable Pin Open-drian
36 PAD_CTL_PE (1 << 0) !! 38 - slew-rate: Integer. Controls Slew Rate
>> 39 0: Standard
>> 40 1: Slow
>> 41 - bias-disable: Bool. Pull disabled
>> 42 - bias-pull-down: Bool. Pull down on pin
>> 43 - bias-pull-up: Bool. Pull up on pin
37 44
38 Examples: 45 Examples:
39 #include "imx7ulp-pinfunc.h" 46 #include "imx7ulp-pinfunc.h"
40 47
41 /* Pin Controller Node */ 48 /* Pin Controller Node */
42 iomuxc1: pinctrl@40ac0000 { !! 49 iomuxc1: iomuxc@40ac0000 {
43 compatible = "fsl,imx7ulp-iomuxc1"; 50 compatible = "fsl,imx7ulp-iomuxc1";
44 reg = <0x40ac0000 0x1000>; 51 reg = <0x40ac0000 0x1000>;
45 52
46 /* Pin Configuration Node */ 53 /* Pin Configuration Node */
47 pinctrl_lpuart4: lpuart4grp { 54 pinctrl_lpuart4: lpuart4grp {
48 fsl,pins = < !! 55 pinmux = <
49 IMX7ULP_PAD_PTC3__LPUA !! 56 IMX7ULP_PAD_PTC3__LPUART4_RX
50 IMX7ULP_PAD_PTC2__LPUA !! 57 IMX7ULP_PAD_PTC2__LPUART4_TX
51 >; 58 >;
>> 59 bias-pull-up;
52 }; 60 };
53 }; 61 };
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