1 * Marvell Armada 370 SoC pinctrl driver for mp 1 * Marvell Armada 370 SoC pinctrl driver for mpp
2 2
3 Please refer to marvell,mvebu-pinctrl.txt in t 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage. 4 part and usage.
5 5
6 Required properties: 6 Required properties:
7 - compatible: "marvell,88f6710-pinctrl" 7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers 8 - reg: register specifier of MPP registers
9 9
10 Available mpp pins/groups and functions: 10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp nam 11 Note: brackets (x) are not part of the mpp name for marvell,function and given
12 only for more detailed description in this doc 12 only for more detailed description in this document.
13 13
14 name pins functions 14 name pins functions
15 ============================================== 15 ================================================================================
16 mpp0 0 gpio, uart0(rxd) 16 mpp0 0 gpio, uart0(rxd)
17 mpp1 1 gpo, uart0(txd) 17 mpp1 1 gpo, uart0(txd)
18 mpp2 2 gpio, i2c0(sck), uart0( 18 mpp2 2 gpio, i2c0(sck), uart0(txd)
19 mpp3 3 gpio, i2c0(sda), uart0( 19 mpp3 3 gpio, i2c0(sda), uart0(rxd)
20 mpp4 4 gpio, vdd(cpu-pd) 20 mpp4 4 gpio, vdd(cpu-pd)
21 mpp5 5 gpo, ge0(txclkout), uar 21 mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
22 mpp6 6 gpio, ge0(txd0), sata0( 22 mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
23 mpp7 7 gpo, ge0(txd1), tdm(dtx 23 mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
24 mpp8 8 gpio, ge0(txd2), uart0( 24 mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
25 mpp9 9 gpo, ge0(txd3), uart1(t 25 mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
26 mpp10 10 gpio, ge0(txctl), uart0 26 mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
27 mpp11 11 gpio, ge0(rxd0), uart1( 27 mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
28 sata1(prsnt), spi1(cs1) 28 sata1(prsnt), spi1(cs1)
29 mpp12 12 gpio, ge0(rxd1), i2c1(s 29 mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
30 audio(spdifi) 30 audio(spdifi)
31 mpp13 13 gpio, ge0(rxd2), i2c1(s 31 mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
32 audio(rmclk) 32 audio(rmclk)
33 mpp14 14 gpio, ge0(rxd3), pcie(c 33 mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
34 spi0(cs2) 34 spi0(cs2)
35 mpp15 15 gpio, ge0(rxctl), pcie( 35 mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
36 spi0(cs3) 36 spi0(cs3)
37 mpp16 16 gpio, ge0(rxclk), uart1 37 mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
38 mpp17 17 gpo, ge(mdc) 38 mpp17 17 gpo, ge(mdc)
39 mpp18 18 gpio, ge(mdio) 39 mpp18 18 gpio, ge(mdio)
40 mpp19 19 gpio, ge0(txclk), ge1(t 40 mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
41 mpp20 20 gpo, ge0(txd4), ge1(txd 41 mpp20 20 gpo, ge0(txd4), ge1(txd0)
42 mpp21 21 gpo, ge0(txd5), ge1(txd 42 mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
43 mpp22 22 gpo, ge0(txd6), ge1(txd 43 mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
44 mpp23 23 gpo, ge0(txd7), ge1(txd 44 mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
45 mpp24 24 gpio, ge0(col), ge1(txc 45 mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
46 mpp25 25 gpio, ge0(rxerr), ge1(r 46 mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
47 mpp26 26 gpio, ge0(crs), ge1(rxd 47 mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
48 mpp27 27 gpio, ge0(rxd4), ge1(rx 48 mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
49 mpp28 28 gpio, ge0(rxd5), ge1(rx 49 mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
50 mpp29 29 gpio, ge0(rxd6), ge1(rx 50 mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
51 mpp30 30 gpio, ge0(rxd7), ge1(rx 51 mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
52 mpp31 31 gpio, tclk, ge0(txerr) 52 mpp31 31 gpio, tclk, ge0(txerr)
53 mpp32 32 gpio, spi0(cs0) 53 mpp32 32 gpio, spi0(cs0)
54 mpp33 33 gpio, dev(bootcs), spi0 54 mpp33 33 gpio, dev(bootcs), spi0(cs0)
55 mpp34 34 gpo, dev(we0), spi0(mos 55 mpp34 34 gpo, dev(we0), spi0(mosi)
56 mpp35 35 gpo, dev(oe), spi0(sck) 56 mpp35 35 gpo, dev(oe), spi0(sck)
57 mpp36 36 gpo, dev(a1), spi0(miso 57 mpp36 36 gpo, dev(a1), spi0(miso)
58 mpp37 37 gpo, dev(a0), sata0(prs 58 mpp37 37 gpo, dev(a0), sata0(prsnt)
59 mpp38 38 gpio, dev(ready), uart1 59 mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
60 mpp39 39 gpo, dev(ad0), audio(sp 60 mpp39 39 gpo, dev(ad0), audio(spdifo)
61 mpp40 40 gpio, dev(ad1), uart1(r 61 mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
62 mpp41 41 gpio, dev(ad2), uart1(r 62 mpp41 41 gpio, dev(ad2), uart1(rxd)
63 mpp42 42 gpo, dev(ad3), uart1(tx 63 mpp42 42 gpo, dev(ad3), uart1(txd)
64 mpp43 43 gpo, dev(ad4), audio(bc 64 mpp43 43 gpo, dev(ad4), audio(bclk)
65 mpp44 44 gpo, dev(ad5), audio(mc 65 mpp44 44 gpo, dev(ad5), audio(mclk)
66 mpp45 45 gpo, dev(ad6), audio(lr 66 mpp45 45 gpo, dev(ad6), audio(lrclk)
67 mpp46 46 gpo, dev(ad7), audio(sd 67 mpp46 46 gpo, dev(ad7), audio(sdo)
68 mpp47 47 gpo, dev(ad8), sd0(clk) 68 mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
69 mpp48 48 gpio, dev(ad9), uart0(r 69 mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
70 spi0(cs1) 70 spi0(cs1)
71 mpp49 49 gpio, dev(ad10), pcie(c 71 mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
72 audio(spdifi) 72 audio(spdifi)
73 mpp50 50 gpio, dev(ad11), uart0( 73 mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
74 audio(rmclk) 74 audio(rmclk)
75 mpp51 51 gpio, dev(ad12), i2c1(s 75 mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
76 mpp52 52 gpio, dev(ad13), i2c1(s 76 mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
77 mpp53 53 gpio, dev(ad14), sd0(cl 77 mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
78 pcie(clkreq1) 78 pcie(clkreq1)
79 mpp54 54 gpo, dev(ad15), tdm(dtx 79 mpp54 54 gpo, dev(ad15), tdm(dtx)
80 mpp55 55 gpio, dev(cs1), uart1(t 80 mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
81 sata0(prsnt) 81 sata0(prsnt)
82 mpp56 56 gpio, dev(cs2), uart1(c 82 mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
83 pcie(clkreq0), spi1(cs1 83 pcie(clkreq0), spi1(cs1)
84 mpp57 57 gpio, dev(cs3), uart1(r 84 mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
85 audio(sdo) 85 audio(sdo)
86 mpp58 58 gpio, dev(cs0), uart1(r 86 mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
87 uart0(rts) 87 uart0(rts)
88 mpp59 59 gpo, dev(ale0), uart1(r 88 mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
89 mpp60 60 gpio, dev(ale1), uart1( 89 mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),
90 audio(sdi) 90 audio(sdi)
91 mpp61 61 gpo, dev(we1), uart1(tx 91 mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
92 mpp62 62 gpio, dev(a2), uart1(ct 92 mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
93 audio(mclk), uart0(cts) 93 audio(mclk), uart0(cts)
94 mpp63 63 gpio, spi0(sck), tclk !! 94 mpp63 63 gpo, spi0(sck), tclk
95 mpp64 64 gpio, spi0(miso), spi0( 95 mpp64 64 gpio, spi0(miso), spi0(cs1)
96 mpp65 65 gpio, spi0(mosi), spi0( 96 mpp65 65 gpio, spi0(mosi), spi0(cs2)
97 <<
98 Note: According to the datasheet mpp63 is a gp <<
99 one example of a gpio usage on the board D-Lin <<
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