1 * Marvell Armada 370 SoC pinctrl driver for mp
2
3 Please refer to marvell,mvebu-pinctrl.txt in t
4 part and usage.
5
6 Required properties:
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
9
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp nam
12 only for more detailed description in this doc
13
14 name pins functions
15 ==============================================
16 mpp0 0 gpio, uart0(rxd)
17 mpp1 1 gpo, uart0(txd)
18 mpp2 2 gpio, i2c0(sck), uart0(
19 mpp3 3 gpio, i2c0(sda), uart0(
20 mpp4 4 gpio, vdd(cpu-pd)
21 mpp5 5 gpo, ge0(txclkout), uar
22 mpp6 6 gpio, ge0(txd0), sata0(
23 mpp7 7 gpo, ge0(txd1), tdm(dtx
24 mpp8 8 gpio, ge0(txd2), uart0(
25 mpp9 9 gpo, ge0(txd3), uart1(t
26 mpp10 10 gpio, ge0(txctl), uart0
27 mpp11 11 gpio, ge0(rxd0), uart1(
28 sata1(prsnt), spi1(cs1)
29 mpp12 12 gpio, ge0(rxd1), i2c1(s
30 audio(spdifi)
31 mpp13 13 gpio, ge0(rxd2), i2c1(s
32 audio(rmclk)
33 mpp14 14 gpio, ge0(rxd3), pcie(c
34 spi0(cs2)
35 mpp15 15 gpio, ge0(rxctl), pcie(
36 spi0(cs3)
37 mpp16 16 gpio, ge0(rxclk), uart1
38 mpp17 17 gpo, ge(mdc)
39 mpp18 18 gpio, ge(mdio)
40 mpp19 19 gpio, ge0(txclk), ge1(t
41 mpp20 20 gpo, ge0(txd4), ge1(txd
42 mpp21 21 gpo, ge0(txd5), ge1(txd
43 mpp22 22 gpo, ge0(txd6), ge1(txd
44 mpp23 23 gpo, ge0(txd7), ge1(txd
45 mpp24 24 gpio, ge0(col), ge1(txc
46 mpp25 25 gpio, ge0(rxerr), ge1(r
47 mpp26 26 gpio, ge0(crs), ge1(rxd
48 mpp27 27 gpio, ge0(rxd4), ge1(rx
49 mpp28 28 gpio, ge0(rxd5), ge1(rx
50 mpp29 29 gpio, ge0(rxd6), ge1(rx
51 mpp30 30 gpio, ge0(rxd7), ge1(rx
52 mpp31 31 gpio, tclk, ge0(txerr)
53 mpp32 32 gpio, spi0(cs0)
54 mpp33 33 gpio, dev(bootcs), spi0
55 mpp34 34 gpo, dev(we0), spi0(mos
56 mpp35 35 gpo, dev(oe), spi0(sck)
57 mpp36 36 gpo, dev(a1), spi0(miso
58 mpp37 37 gpo, dev(a0), sata0(prs
59 mpp38 38 gpio, dev(ready), uart1
60 mpp39 39 gpo, dev(ad0), audio(sp
61 mpp40 40 gpio, dev(ad1), uart1(r
62 mpp41 41 gpio, dev(ad2), uart1(r
63 mpp42 42 gpo, dev(ad3), uart1(tx
64 mpp43 43 gpo, dev(ad4), audio(bc
65 mpp44 44 gpo, dev(ad5), audio(mc
66 mpp45 45 gpo, dev(ad6), audio(lr
67 mpp46 46 gpo, dev(ad7), audio(sd
68 mpp47 47 gpo, dev(ad8), sd0(clk)
69 mpp48 48 gpio, dev(ad9), uart0(r
70 spi0(cs1)
71 mpp49 49 gpio, dev(ad10), pcie(c
72 audio(spdifi)
73 mpp50 50 gpio, dev(ad11), uart0(
74 audio(rmclk)
75 mpp51 51 gpio, dev(ad12), i2c1(s
76 mpp52 52 gpio, dev(ad13), i2c1(s
77 mpp53 53 gpio, dev(ad14), sd0(cl
78 pcie(clkreq1)
79 mpp54 54 gpo, dev(ad15), tdm(dtx
80 mpp55 55 gpio, dev(cs1), uart1(t
81 sata0(prsnt)
82 mpp56 56 gpio, dev(cs2), uart1(c
83 pcie(clkreq0), spi1(cs1
84 mpp57 57 gpio, dev(cs3), uart1(r
85 audio(sdo)
86 mpp58 58 gpio, dev(cs0), uart1(r
87 uart0(rts)
88 mpp59 59 gpo, dev(ale0), uart1(r
89 mpp60 60 gpio, dev(ale1), uart1(
90 audio(sdi)
91 mpp61 61 gpo, dev(we1), uart1(tx
92 mpp62 62 gpio, dev(a2), uart1(ct
93 audio(mclk), uart0(cts)
94 mpp63 63 gpio, spi0(sck), tclk
95 mpp64 64 gpio, spi0(miso), spi0(
96 mpp65 65 gpio, spi0(mosi), spi0(
97
98 Note: According to the datasheet mpp63 is a gp
99 one example of a gpio usage on the board D-Lin
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