1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/med 4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek MT65xx Pin Controller !! 7 title: Mediatek MT65xx Pin Controller Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Sean Wang <sean.wang@kernel.org> 10 - Sean Wang <sean.wang@kernel.org>
11 11
12 description: !! 12 description: |+
13 The MediaTek's MT65xx Pin controller is used !! 13 The Mediatek's Pin controller is used to control SoC pins.
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 enum: 17 enum:
18 - mediatek,mt2701-pinctrl 18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl 19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl 20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl 21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl 22 - mediatek,mt8127-pinctrl
23 - mediatek,mt8135-pinctrl 23 - mediatek,mt8135-pinctrl
24 - mediatek,mt8167-pinctrl 24 - mediatek,mt8167-pinctrl
25 - mediatek,mt8173-pinctrl 25 - mediatek,mt8173-pinctrl
26 - mediatek,mt8516-pinctrl 26 - mediatek,mt8516-pinctrl
27 27
28 reg: 28 reg:
29 maxItems: 1 29 maxItems: 1
30 30
31 pins-are-numbered: 31 pins-are-numbered:
32 $ref: /schemas/types.yaml#/definitions/fla 32 $ref: /schemas/types.yaml#/definitions/flag
33 description: !! 33 description: |
34 Specify the subnodes are using numbered !! 34 Specify the subnodes are using numbered pinmux to specify pins.
35 deprecated: true <<
36 35
37 gpio-controller: true 36 gpio-controller: true
38 37
39 "#gpio-cells": 38 "#gpio-cells":
40 const: 2 39 const: 2
41 description: !! 40 description: |
42 Number of cells in GPIO specifier. Since !! 41 Number of cells in GPIO specifier. Since the generic GPIO
43 the amount of cells must be specified as !! 42 binding is used, the amount of cells must be specified as 2. See the below
44 binding representation for description o !! 43 mentioned gpio binding representation for description of particular cells.
45 44
46 mediatek,pctl-regmap: 45 mediatek,pctl-regmap:
47 $ref: /schemas/types.yaml#/definitions/pha 46 $ref: /schemas/types.yaml#/definitions/phandle-array
48 items: <<
49 maxItems: 1 <<
50 minItems: 1 47 minItems: 1
51 maxItems: 2 48 maxItems: 2
52 description: !! 49 description: |
53 Should be phandles of the syscfg node. 50 Should be phandles of the syscfg node.
54 51
55 interrupt-controller: true 52 interrupt-controller: true
56 53
57 interrupts: 54 interrupts:
58 minItems: 1 55 minItems: 1
59 maxItems: 3 56 maxItems: 3
60 57
61 "#interrupt-cells": 58 "#interrupt-cells":
62 const: 2 59 const: 2
63 60
64 required: 61 required:
65 - compatible 62 - compatible
>> 63 - pins-are-numbered
66 - gpio-controller 64 - gpio-controller
67 - "#gpio-cells" 65 - "#gpio-cells"
68 66
69 allOf: 67 allOf:
70 - $ref: pinctrl.yaml# !! 68 - $ref: "pinctrl.yaml#"
71 69
72 patternProperties: 70 patternProperties:
73 'pins$': !! 71 '-[0-9]+$':
74 type: object 72 type: object
75 additionalProperties: false 73 additionalProperties: false
76 patternProperties: 74 patternProperties:
77 '(^pins|pins?$)': !! 75 'pins':
78 type: object 76 type: object
79 additionalProperties: false 77 additionalProperties: false
80 description: !! 78 description: |
81 A pinctrl node should contain at lea 79 A pinctrl node should contain at least one subnodes representing the
82 pinctrl groups available on the mach 80 pinctrl groups available on the machine. Each subnode will list the
83 pins it needs, and how they should b 81 pins it needs, and how they should be configured, with regard to muxer
84 configuration, pullups, drive streng 82 configuration, pullups, drive strength, input enable/disable and input
85 schmitt. 83 schmitt.
86 $ref: /schemas/pinctrl/pincfg-node.yam !! 84 $ref: "/schemas/pinctrl/pincfg-node.yaml"
87 85
88 properties: 86 properties:
89 pinmux: 87 pinmux:
90 description: 88 description:
91 Integer array, represents gpio p !! 89 integer array, represents gpio pin number and mux setting.
92 Supported pin number and mux var 90 Supported pin number and mux varies for different SoCs, and are
93 defined as macros in dt-bindings !! 91 defined as macros in <soc>-pinfunc.h directly.
94 92
95 bias-disable: true 93 bias-disable: true
96 94
97 bias-pull-up: 95 bias-pull-up:
98 description: !! 96 description: |
99 Besides generic pinconfig option 97 Besides generic pinconfig options, it can be used as the pull up
100 settings for 2 pull resistors, R 98 settings for 2 pull resistors, R0 and R1. User can configure those
101 special pins. Some macros have b 99 special pins. Some macros have been defined for this usage, such
102 as MTK_PUPD_SET_R1R0_00. See dt- 100 as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
103 valid arguments. 101 valid arguments.
104 102
105 bias-pull-down: true 103 bias-pull-down: true
106 104
107 input-enable: true 105 input-enable: true
108 106
109 input-disable: true 107 input-disable: true
110 108
111 output-low: true 109 output-low: true
112 110
113 output-high: true 111 output-high: true
114 112
115 input-schmitt-enable: true 113 input-schmitt-enable: true
116 114
117 input-schmitt-disable: true 115 input-schmitt-disable: true
118 116
119 drive-strength: 117 drive-strength:
120 description: !! 118 description: |
121 Can support some arguments, such 119 Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
122 etc. See dt-bindings/pinctrl/mt6 120 etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
123 121
124 required: 122 required:
125 - pinmux 123 - pinmux
126 124
127 additionalProperties: false 125 additionalProperties: false
128 126
129 examples: 127 examples:
130 - | 128 - |
131 #include <dt-bindings/interrupt-controller 129 #include <dt-bindings/interrupt-controller/irq.h>
132 #include <dt-bindings/interrupt-controller 130 #include <dt-bindings/interrupt-controller/arm-gic.h>
133 #include <dt-bindings/pinctrl/mt8135-pinfu 131 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
134 132
135 soc { 133 soc {
136 #address-cells = <2>; 134 #address-cells = <2>;
137 #size-cells = <2>; 135 #size-cells = <2>;
138 136
139 syscfg_pctl_a: syscfg-pctl-a@10005000 137 syscfg_pctl_a: syscfg-pctl-a@10005000 {
140 compatible = "mediatek,mt8135-pctl-a 138 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
141 reg = <0 0x10005000 0 0x1000>; 139 reg = <0 0x10005000 0 0x1000>;
142 }; 140 };
143 141
144 syscfg_pctl_b: syscfg-pctl-b@1020c020 142 syscfg_pctl_b: syscfg-pctl-b@1020c020 {
145 compatible = "mediatek,mt8135-pctl-b 143 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
146 reg = <0 0x1020C020 0 0x1000>; 144 reg = <0 0x1020C020 0 0x1000>;
147 }; 145 };
148 146
149 pinctrl@1c20800 { 147 pinctrl@1c20800 {
150 compatible = "mediatek,mt8135-pinctr 148 compatible = "mediatek,mt8135-pinctrl";
151 reg = <0 0x1000B000 0 0x1000>; 149 reg = <0 0x1000B000 0 0x1000>;
152 mediatek,pctl-regmap = <&syscfg_pctl 150 mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
>> 151 pins-are-numbered;
153 gpio-controller; 152 gpio-controller;
154 #gpio-cells = <2>; 153 #gpio-cells = <2>;
155 interrupt-controller; 154 interrupt-controller;
156 #interrupt-cells = <2>; 155 #interrupt-cells = <2>;
157 interrupts = <GIC_SPI 116 IRQ_TYPE_L 156 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 157 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 158 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
160 159
161 i2c0_pins_a: i2c0-pins { !! 160 i2c0_pins_a: i2c0-0 {
162 pins1 { 161 pins1 {
163 pinmux = <MT8135_PIN_100_SDA0__F 162 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
164 <MT8135_PIN_101_SCL0__FUNC_SCL 163 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
165 bias-disable; 164 bias-disable;
166 }; 165 };
167 }; 166 };
168 167
169 i2c1_pins_a: i2c1-pins { !! 168 i2c1_pins_a: i2c1-0 {
170 pins { 169 pins {
171 pinmux = <MT8135_PIN_195_SDA1__F 170 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
172 <MT8135_PIN_196_SCL1__FUNC_SCL 171 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
173 bias-pull-up = <MTK_PUPD_SET_R1R 172 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
174 }; 173 };
175 }; 174 };
176 175
177 i2c2_pins_a: i2c2-pins { !! 176 i2c2_pins_a: i2c2-0 {
178 pins1 { 177 pins1 {
179 pinmux = <MT8135_PIN_193_SDA2__F 178 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
180 bias-pull-down; 179 bias-pull-down;
181 }; 180 };
182 181
183 pins2 { 182 pins2 {
184 pinmux = <MT8135_PIN_49_WATCHDOG 183 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
185 bias-pull-up; 184 bias-pull-up;
186 }; 185 };
187 }; 186 };
188 187
189 i2c3_pins_a: i2c3-pins { !! 188 i2c3_pins_a: i2c3-0 {
190 pins1 { 189 pins1 {
191 pinmux = <MT8135_PIN_40_DAC_CLK_ 190 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
192 <MT8135_PIN_41_DAC_WS__FUNC_GP 191 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
193 bias-pull-up = <MTK_PUPD_SET_R1R 192 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
194 }; 193 };
195 194
196 pins2 { 195 pins2 {
197 pinmux = <MT8135_PIN_35_SCL3__FU 196 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
198 <MT8135_PIN_36_SDA3__FUNC_SDA3 197 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
199 output-low; 198 output-low;
200 bias-pull-up = <MTK_PUPD_SET_R1R 199 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
201 }; 200 };
202 201
203 pins3 { 202 pins3 {
204 pinmux = <MT8135_PIN_57_JTCK__FU 203 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
205 <MT8135_PIN_60_JTDI__FUNC_JTDI 204 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
206 drive-strength = <32>; 205 drive-strength = <32>;
207 }; 206 };
208 }; 207 };
209 }; 208 };
210 }; 209 };
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