1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/med 4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek MT65xx Pin Controller !! 7 title: Mediatek MT65xx Pin Controller Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Sean Wang <sean.wang@kernel.org> 10 - Sean Wang <sean.wang@kernel.org>
11 11
12 description: !! 12 description: |+
13 The MediaTek's MT65xx Pin controller is used !! 13 The Mediatek's Pin controller is used to control SoC pins.
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 enum: 17 enum:
18 - mediatek,mt2701-pinctrl 18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl 19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl 20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl 21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl 22 - mediatek,mt8127-pinctrl
23 - mediatek,mt8135-pinctrl 23 - mediatek,mt8135-pinctrl
24 - mediatek,mt8167-pinctrl 24 - mediatek,mt8167-pinctrl
25 - mediatek,mt8173-pinctrl 25 - mediatek,mt8173-pinctrl
26 - mediatek,mt8516-pinctrl 26 - mediatek,mt8516-pinctrl
27 27
28 reg: 28 reg:
29 maxItems: 1 29 maxItems: 1
30 30
31 pins-are-numbered: 31 pins-are-numbered:
32 $ref: /schemas/types.yaml#/definitions/fla 32 $ref: /schemas/types.yaml#/definitions/flag
33 description: !! 33 description: |
34 Specify the subnodes are using numbered !! 34 Specify the subnodes are using numbered pinmux to specify pins.
35 deprecated: true <<
36 35
37 gpio-controller: true 36 gpio-controller: true
38 37
39 "#gpio-cells": 38 "#gpio-cells":
40 const: 2 39 const: 2
41 description: !! 40 description: |
42 Number of cells in GPIO specifier. Since !! 41 Number of cells in GPIO specifier. Since the generic GPIO
43 the amount of cells must be specified as !! 42 binding is used, the amount of cells must be specified as 2. See the below
44 binding representation for description o !! 43 mentioned gpio binding representation for description of particular cells.
45 44
46 mediatek,pctl-regmap: 45 mediatek,pctl-regmap:
47 $ref: /schemas/types.yaml#/definitions/pha 46 $ref: /schemas/types.yaml#/definitions/phandle-array
48 items: 47 items:
49 maxItems: 1 48 maxItems: 1
50 minItems: 1 49 minItems: 1
51 maxItems: 2 50 maxItems: 2
52 description: !! 51 description: |
53 Should be phandles of the syscfg node. 52 Should be phandles of the syscfg node.
54 53
55 interrupt-controller: true 54 interrupt-controller: true
56 55
57 interrupts: 56 interrupts:
58 minItems: 1 57 minItems: 1
59 maxItems: 3 58 maxItems: 3
60 59
61 "#interrupt-cells": 60 "#interrupt-cells":
62 const: 2 61 const: 2
63 62
64 required: 63 required:
65 - compatible 64 - compatible
>> 65 - pins-are-numbered
66 - gpio-controller 66 - gpio-controller
67 - "#gpio-cells" 67 - "#gpio-cells"
68 68
69 allOf: 69 allOf:
70 - $ref: pinctrl.yaml# !! 70 - $ref: "pinctrl.yaml#"
71 71
72 patternProperties: 72 patternProperties:
73 'pins$': !! 73 '-[0-9]+$':
74 type: object 74 type: object
75 additionalProperties: false 75 additionalProperties: false
76 patternProperties: 76 patternProperties:
77 '(^pins|pins?$)': !! 77 'pins':
78 type: object 78 type: object
79 additionalProperties: false 79 additionalProperties: false
80 description: !! 80 description: |
81 A pinctrl node should contain at lea 81 A pinctrl node should contain at least one subnodes representing the
82 pinctrl groups available on the mach 82 pinctrl groups available on the machine. Each subnode will list the
83 pins it needs, and how they should b 83 pins it needs, and how they should be configured, with regard to muxer
84 configuration, pullups, drive streng 84 configuration, pullups, drive strength, input enable/disable and input
85 schmitt. 85 schmitt.
86 $ref: /schemas/pinctrl/pincfg-node.yam !! 86 $ref: "/schemas/pinctrl/pincfg-node.yaml"
87 87
88 properties: 88 properties:
89 pinmux: 89 pinmux:
90 description: 90 description:
91 Integer array, represents gpio p !! 91 integer array, represents gpio pin number and mux setting.
92 Supported pin number and mux var 92 Supported pin number and mux varies for different SoCs, and are
93 defined as macros in dt-bindings !! 93 defined as macros in <soc>-pinfunc.h directly.
94 94
95 bias-disable: true 95 bias-disable: true
96 96
97 bias-pull-up: 97 bias-pull-up:
98 description: !! 98 description: |
99 Besides generic pinconfig option 99 Besides generic pinconfig options, it can be used as the pull up
100 settings for 2 pull resistors, R 100 settings for 2 pull resistors, R0 and R1. User can configure those
101 special pins. Some macros have b 101 special pins. Some macros have been defined for this usage, such
102 as MTK_PUPD_SET_R1R0_00. See dt- 102 as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
103 valid arguments. 103 valid arguments.
104 104
105 bias-pull-down: true 105 bias-pull-down: true
106 106
107 input-enable: true 107 input-enable: true
108 108
109 input-disable: true 109 input-disable: true
110 110
111 output-low: true 111 output-low: true
112 112
113 output-high: true 113 output-high: true
114 114
115 input-schmitt-enable: true 115 input-schmitt-enable: true
116 116
117 input-schmitt-disable: true 117 input-schmitt-disable: true
118 118
119 drive-strength: 119 drive-strength:
120 description: !! 120 description: |
121 Can support some arguments, such 121 Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
122 etc. See dt-bindings/pinctrl/mt6 122 etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
123 123
124 required: 124 required:
125 - pinmux 125 - pinmux
126 126
127 additionalProperties: false 127 additionalProperties: false
128 128
129 examples: 129 examples:
130 - | 130 - |
131 #include <dt-bindings/interrupt-controller 131 #include <dt-bindings/interrupt-controller/irq.h>
132 #include <dt-bindings/interrupt-controller 132 #include <dt-bindings/interrupt-controller/arm-gic.h>
133 #include <dt-bindings/pinctrl/mt8135-pinfu 133 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
134 134
135 soc { 135 soc {
136 #address-cells = <2>; 136 #address-cells = <2>;
137 #size-cells = <2>; 137 #size-cells = <2>;
138 138
139 syscfg_pctl_a: syscfg-pctl-a@10005000 139 syscfg_pctl_a: syscfg-pctl-a@10005000 {
140 compatible = "mediatek,mt8135-pctl-a 140 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
141 reg = <0 0x10005000 0 0x1000>; 141 reg = <0 0x10005000 0 0x1000>;
142 }; 142 };
143 143
144 syscfg_pctl_b: syscfg-pctl-b@1020c020 144 syscfg_pctl_b: syscfg-pctl-b@1020c020 {
145 compatible = "mediatek,mt8135-pctl-b 145 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
146 reg = <0 0x1020C020 0 0x1000>; 146 reg = <0 0x1020C020 0 0x1000>;
147 }; 147 };
148 148
149 pinctrl@1c20800 { 149 pinctrl@1c20800 {
150 compatible = "mediatek,mt8135-pinctr 150 compatible = "mediatek,mt8135-pinctrl";
151 reg = <0 0x1000B000 0 0x1000>; 151 reg = <0 0x1000B000 0 0x1000>;
152 mediatek,pctl-regmap = <&syscfg_pctl 152 mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
>> 153 pins-are-numbered;
153 gpio-controller; 154 gpio-controller;
154 #gpio-cells = <2>; 155 #gpio-cells = <2>;
155 interrupt-controller; 156 interrupt-controller;
156 #interrupt-cells = <2>; 157 #interrupt-cells = <2>;
157 interrupts = <GIC_SPI 116 IRQ_TYPE_L 158 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 159 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
160 161
161 i2c0_pins_a: i2c0-pins { !! 162 i2c0_pins_a: i2c0-0 {
162 pins1 { 163 pins1 {
163 pinmux = <MT8135_PIN_100_SDA0__F 164 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
164 <MT8135_PIN_101_SCL0__FUNC_SCL 165 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
165 bias-disable; 166 bias-disable;
166 }; 167 };
167 }; 168 };
168 169
169 i2c1_pins_a: i2c1-pins { !! 170 i2c1_pins_a: i2c1-0 {
170 pins { 171 pins {
171 pinmux = <MT8135_PIN_195_SDA1__F 172 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
172 <MT8135_PIN_196_SCL1__FUNC_SCL 173 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
173 bias-pull-up = <MTK_PUPD_SET_R1R 174 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
174 }; 175 };
175 }; 176 };
176 177
177 i2c2_pins_a: i2c2-pins { !! 178 i2c2_pins_a: i2c2-0 {
178 pins1 { 179 pins1 {
179 pinmux = <MT8135_PIN_193_SDA2__F 180 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
180 bias-pull-down; 181 bias-pull-down;
181 }; 182 };
182 183
183 pins2 { 184 pins2 {
184 pinmux = <MT8135_PIN_49_WATCHDOG 185 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
185 bias-pull-up; 186 bias-pull-up;
186 }; 187 };
187 }; 188 };
188 189
189 i2c3_pins_a: i2c3-pins { !! 190 i2c3_pins_a: i2c3-0 {
190 pins1 { 191 pins1 {
191 pinmux = <MT8135_PIN_40_DAC_CLK_ 192 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
192 <MT8135_PIN_41_DAC_WS__FUNC_GP 193 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
193 bias-pull-up = <MTK_PUPD_SET_R1R 194 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
194 }; 195 };
195 196
196 pins2 { 197 pins2 {
197 pinmux = <MT8135_PIN_35_SCL3__FU 198 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
198 <MT8135_PIN_36_SDA3__FUNC_SDA3 199 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
199 output-low; 200 output-low;
200 bias-pull-up = <MTK_PUPD_SET_R1R 201 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
201 }; 202 };
202 203
203 pins3 { 204 pins3 {
204 pinmux = <MT8135_PIN_57_JTCK__FU 205 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
205 <MT8135_PIN_60_JTDI__FUNC_JTDI 206 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
206 drive-strength = <32>; 207 drive-strength = <32>;
207 }; 208 };
208 }; 209 };
209 }; 210 };
210 }; 211 };
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