1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/med 4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek MT6795 Pin Controller 7 title: MediaTek MT6795 Pin Controller
8 8
9 maintainers: 9 maintainers:
10 - AngeloGioacchino Del Regno <angelogioacchin 10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org> 11 - Sean Wang <sean.wang@kernel.org>
12 12
13 description: 13 description:
14 The MediaTek's MT6795 Pin controller is used 14 The MediaTek's MT6795 Pin controller is used to control SoC pins.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 const: mediatek,mt6795-pinctrl 18 const: mediatek,mt6795-pinctrl
19 19
20 gpio-controller: true 20 gpio-controller: true
21 21
22 '#gpio-cells': 22 '#gpio-cells':
23 description: 23 description:
24 Number of cells in GPIO specifier. Since 24 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
25 the amount of cells must be specified as 25 the amount of cells must be specified as 2. See the below mentioned gpio
26 binding representation for description o 26 binding representation for description of particular cells.
27 const: 2 27 const: 2
28 28
29 gpio-ranges: 29 gpio-ranges:
30 description: GPIO valid number range. 30 description: GPIO valid number range.
31 maxItems: 1 31 maxItems: 1
32 32
33 reg: 33 reg:
34 description: 34 description:
35 Physical address base for GPIO base and 35 Physical address base for GPIO base and eint registers.
36 minItems: 2 36 minItems: 2
37 37
38 reg-names: 38 reg-names:
39 items: 39 items:
40 - const: base 40 - const: base
41 - const: eint 41 - const: eint
42 42
43 interrupt-controller: true 43 interrupt-controller: true
44 44
45 '#interrupt-cells': 45 '#interrupt-cells':
46 const: 2 46 const: 2
47 47
48 interrupts: 48 interrupts:
49 description: Interrupt outputs to the syst 49 description: Interrupt outputs to the system interrupt controller (sysirq).
50 minItems: 1 50 minItems: 1
51 items: 51 items:
52 - description: EINT interrupt 52 - description: EINT interrupt
53 - description: EINT event_b interrupt 53 - description: EINT event_b interrupt
54 54
55 # PIN CONFIGURATION NODES 55 # PIN CONFIGURATION NODES
56 patternProperties: 56 patternProperties:
57 '-pins$': 57 '-pins$':
58 type: object 58 type: object
59 additionalProperties: false 59 additionalProperties: false
60 patternProperties: 60 patternProperties:
61 '^pins': 61 '^pins':
62 type: object 62 type: object
63 additionalProperties: false 63 additionalProperties: false
64 description: | 64 description: |
65 A pinctrl node should contain at lea 65 A pinctrl node should contain at least one subnodes representing the
66 pinctrl groups available on the mach 66 pinctrl groups available on the machine. Each subnode will list the
67 pins it needs, and how they should b 67 pins it needs, and how they should be configured, with regard to muxer
68 configuration, pullups, drive streng 68 configuration, pullups, drive strength, input enable/disable and input
69 schmitt. 69 schmitt.
70 An example of using macro: 70 An example of using macro:
71 pincontroller { 71 pincontroller {
72 /* GPIO0 set as multifunction GPIO 72 /* GPIO0 set as multifunction GPIO0 */
73 gpio-pins { 73 gpio-pins {
74 pins { 74 pins {
75 pinmux = <PINMUX_GPIO0__FUNC_G 75 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
76 } 76 }
77 }; 77 };
78 /* GPIO45 set as multifunction SDA 78 /* GPIO45 set as multifunction SDA0 */
79 i2c0-pins { 79 i2c0-pins {
80 pins { 80 pins {
81 pinmux = <PINMUX_GPIO45__FUNC_ 81 pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
82 } 82 }
83 }; 83 };
84 }; 84 };
85 $ref: pinmux-node.yaml 85 $ref: pinmux-node.yaml
86 86
87 properties: 87 properties:
88 pinmux: 88 pinmux:
89 description: 89 description:
90 Integer array, represents gpio p 90 Integer array, represents gpio pin number and mux setting.
91 Supported pin number and mux var 91 Supported pin number and mux varies for different SoCs, and are
92 defined as macros in dt-bindings 92 defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
93 93
94 drive-strength: 94 drive-strength:
95 enum: [2, 4, 6, 8, 10, 12, 14, 16] 95 enum: [2, 4, 6, 8, 10, 12, 14, 16]
96 96
97 bias-pull-down: 97 bias-pull-down:
98 oneOf: 98 oneOf:
99 - type: boolean 99 - type: boolean
100 - enum: [100, 101, 102, 103] 100 - enum: [100, 101, 102, 103]
101 description: mt6795 pull down 101 description: mt6795 pull down PUPD/R0/R1 type define value.
102 description: 102 description:
103 For normal pull down type, it is 103 For normal pull down type, it is not necessary to specify R1R0
104 values; When pull down type is P 104 values; When pull down type is PUPD/R0/R1, adding R1R0 defines
105 will set different resistance va 105 will set different resistance values.
106 106
107 bias-pull-up: 107 bias-pull-up:
108 oneOf: 108 oneOf:
109 - type: boolean 109 - type: boolean
110 - enum: [100, 101, 102, 103] 110 - enum: [100, 101, 102, 103]
111 description: mt6795 pull up PU 111 description: mt6795 pull up PUPD/R0/R1 type define value.
112 description: 112 description:
113 For normal pull up type, it is n 113 For normal pull up type, it is not necessary to specify R1R0
114 values; When pull up type is PUP 114 values; When pull up type is PUPD/R0/R1, adding R1R0 defines will
115 set different resistance values. 115 set different resistance values.
116 116
117 bias-disable: true 117 bias-disable: true
118 118
119 output-high: true 119 output-high: true
120 120
121 output-low: true 121 output-low: true
122 122
123 input-enable: true 123 input-enable: true
124 124
125 input-disable: true 125 input-disable: true
126 126
127 input-schmitt-enable: true 127 input-schmitt-enable: true
128 128
129 input-schmitt-disable: true 129 input-schmitt-disable: true
130 130
131 mediatek,pull-up-adv: 131 mediatek,pull-up-adv:
132 description: | 132 description: |
133 Pull up settings for 2 pull resi !! 133 Pull up setings for 2 pull resistors, R0 and R1. User can
134 configure those special pins. Va 134 configure those special pins. Valid arguments are described as
135 below: 135 below:
136 0: (R1, R0) = (0, 0) which means 136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
137 1: (R1, R0) = (0, 1) which means 137 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
138 2: (R1, R0) = (1, 0) which means 138 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
139 3: (R1, R0) = (1, 1) which means 139 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
140 $ref: /schemas/types.yaml#/definit 140 $ref: /schemas/types.yaml#/definitions/uint32
141 enum: [0, 1, 2, 3] 141 enum: [0, 1, 2, 3]
142 142
143 mediatek,pull-down-adv: 143 mediatek,pull-down-adv:
144 description: | 144 description: |
145 Pull down settings for 2 pull re 145 Pull down settings for 2 pull resistors, R0 and R1. User can
146 configure those special pins. Va 146 configure those special pins. Valid arguments are described as
147 below: 147 below:
148 0: (R1, R0) = (0, 0) which means 148 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
149 1: (R1, R0) = (0, 1) which means 149 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
150 2: (R1, R0) = (1, 0) which means 150 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
151 3: (R1, R0) = (1, 1) which means 151 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
152 $ref: /schemas/types.yaml#/definit 152 $ref: /schemas/types.yaml#/definitions/uint32
153 enum: [0, 1, 2, 3] 153 enum: [0, 1, 2, 3]
154 154
155 required: 155 required:
156 - pinmux 156 - pinmux
157 157
158 allOf: 158 allOf:
159 - $ref: pinctrl.yaml# 159 - $ref: pinctrl.yaml#
160 160
161 required: 161 required:
162 - compatible 162 - compatible
163 - reg 163 - reg
164 - reg-names 164 - reg-names
165 - interrupts 165 - interrupts
166 - interrupt-controller 166 - interrupt-controller
167 - '#interrupt-cells' 167 - '#interrupt-cells'
168 - gpio-controller 168 - gpio-controller
169 - '#gpio-cells' 169 - '#gpio-cells'
170 - gpio-ranges 170 - gpio-ranges
171 171
172 additionalProperties: false 172 additionalProperties: false
173 173
174 examples: 174 examples:
175 - | 175 - |
176 #include <dt-bindings/interrupt-controller 176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/interrupt-controller 177 #include <dt-bindings/interrupt-controller/irq.h>
178 #include <dt-bindings/pinctrl/mt6795-pinfu 178 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
179 179
180 soc { 180 soc {
181 #address-cells = <2>; 181 #address-cells = <2>;
182 #size-cells = <2>; 182 #size-cells = <2>;
183 183
184 pio: pinctrl@10005000 { 184 pio: pinctrl@10005000 {
185 compatible = "mediatek,mt6795-pinc 185 compatible = "mediatek,mt6795-pinctrl";
186 reg = <0 0x10005000 0 0x1000>, <0 186 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
187 reg-names = "base", "eint"; 187 reg-names = "base", "eint";
188 gpio-controller; 188 gpio-controller;
189 #gpio-cells = <2>; 189 #gpio-cells = <2>;
190 gpio-ranges = <&pio 0 0 196>; 190 gpio-ranges = <&pio 0 0 196>;
191 interrupt-controller; 191 interrupt-controller;
192 interrupts = <GIC_SPI 153 IRQ_TYPE 192 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
193 #interrupt-cells = <2>; 193 #interrupt-cells = <2>;
194 194
195 i2c0-pins { 195 i2c0-pins {
196 pins-sda-scl { 196 pins-sda-scl {
197 pinmux = <PINMUX_GPIO45__F 197 pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
198 <PINMUX_GPIO46__F 198 <PINMUX_GPIO46__FUNC_SCL0>;
199 }; 199 };
200 }; 200 };
201 201
202 mmc0-pins { 202 mmc0-pins {
203 pins-cmd-dat { 203 pins-cmd-dat {
204 pinmux = <PINMUX_GPIO154__ 204 pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
205 <PINMUX_GPIO155__ 205 <PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
206 <PINMUX_GPIO156__ 206 <PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
207 <PINMUX_GPIO157__ 207 <PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
208 <PINMUX_GPIO158__ 208 <PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
209 <PINMUX_GPIO159__ 209 <PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
210 <PINMUX_GPIO160__ 210 <PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
211 <PINMUX_GPIO161__ 211 <PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
212 <PINMUX_GPIO162__ 212 <PINMUX_GPIO162__FUNC_MSDC0_CMD>;
213 input-enable; 213 input-enable;
214 bias-pull-up = <MTK_PUPD_S 214 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
215 }; 215 };
216 216
217 pins-clk { 217 pins-clk {
218 pinmux = <PINMUX_GPIO163__ 218 pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
219 bias-pull-down = <MTK_PUPD 219 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
220 }; 220 };
221 221
222 pins-rst { 222 pins-rst {
223 pinmux = <PINMUX_GPIO165__ 223 pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
224 bias-pull-up = <MTK_PUPD_S 224 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
225 }; 225 };
226 }; 226 };
227 }; 227 };
228 }; 228 };
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