1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/med
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: MediaTek MT8183 Pin Controller
8
9 maintainers:
10 - Sean Wang <sean.wang@kernel.org>
11
12 description:
13 The MediaTek's MT8183 Pin controller is used
14
15 properties:
16 compatible:
17 const: mediatek,mt8183-pinctrl
18
19 reg:
20 minItems: 10
21 maxItems: 10
22
23 reg-names:
24 items:
25 - const: iocfg0
26 - const: iocfg1
27 - const: iocfg2
28 - const: iocfg3
29 - const: iocfg4
30 - const: iocfg5
31 - const: iocfg6
32 - const: iocfg7
33 - const: iocfg8
34 - const: eint
35
36 gpio-controller: true
37
38 "#gpio-cells":
39 const: 2
40 description:
41 Number of cells in GPIO specifier. Since
42 the amount of cells must be specified as
43 binding representation for description o
44
45 gpio-ranges:
46 minItems: 1
47 maxItems: 5
48 description:
49 GPIO valid number range.
50
51 interrupt-controller: true
52
53 interrupts:
54 maxItems: 1
55
56 "#interrupt-cells":
57 const: 2
58
59 allOf:
60 - $ref: pinctrl.yaml#
61
62 required:
63 - compatible
64 - reg
65 - gpio-controller
66 - "#gpio-cells"
67 - gpio-ranges
68
69 patternProperties:
70 '-pins(-[a-z]+)?$':
71 type: object
72 additionalProperties: false
73 patternProperties:
74 '^pins':
75 type: object
76 additionalProperties: false
77 description:
78 A pinctrl node should contain at lea
79 pinctrl groups available on the mach
80 pins it needs, and how they should b
81 configuration, pullups, drive streng
82 schmitt.
83 $ref: /schemas/pinctrl/pincfg-node.yam
84
85 properties:
86 pinmux:
87 description:
88 Integer array, represents gpio p
89 Supported pin number and mux var
90 defined as macros in <soc>-pinfu
91
92 bias-disable: true
93
94 bias-pull-up: true
95
96 bias-pull-down: true
97
98 input-enable: true
99
100 input-disable: true
101
102 output-low: true
103
104 output-high: true
105
106 input-schmitt-enable: true
107
108 input-schmitt-disable: true
109
110 drive-strength:
111 enum: [2, 4, 6, 8, 10, 12, 14, 16]
112
113 drive-strength-microamp:
114 enum: [125, 250, 500, 1000]
115
116 mediatek,drive-strength-adv:
117 deprecated: true
118 description: |
119 DEPRECATED: Please use drive-str
120 Describe the specific driving se
121 For I2C pins, the existing gener
122 2/4/6/8/10/12/14/16mA driving. B
123 can support 0.125/0.25/0.5/1mA a
124 driving setup, the existing gene
125 The specific driving setup is co
126 When E1=0/E0=0, the strength is
127 When E1=0/E0=1, the strength is
128 When E1=1/E0=0, the strength is
129 When E1=1/E0=1, the strength is
130 EN is used to enable or disable
131 Valid arguments are described as
132 0: (E1, E0, EN) = (0, 0, 0)
133 1: (E1, E0, EN) = (0, 0, 1)
134 2: (E1, E0, EN) = (0, 1, 0)
135 3: (E1, E0, EN) = (0, 1, 1)
136 4: (E1, E0, EN) = (1, 0, 0)
137 5: (E1, E0, EN) = (1, 0, 1)
138 6: (E1, E0, EN) = (1, 1, 0)
139 7: (E1, E0, EN) = (1, 1, 1)
140 So the valid arguments are from
141 $ref: /schemas/types.yaml#/definit
142 enum: [0, 1, 2, 3, 4, 5, 6, 7]
143
144 mediatek,pull-up-adv:
145 description: |
146 Pull up settings for 2 pull resi
147 configure those special pins. Va
148 below:
149 0: (R1, R0) = (0, 0) which means
150 1: (R1, R0) = (0, 1) which means
151 2: (R1, R0) = (1, 0) which means
152 3: (R1, R0) = (1, 1) which means
153 $ref: /schemas/types.yaml#/definit
154 enum: [0, 1, 2, 3]
155
156 mediatek,pull-down-adv:
157 description: |
158 Pull down settings for 2 pull re
159 configure those special pins. Va
160 below:
161 0: (R1, R0) = (0, 0) which means
162 1: (R1, R0) = (0, 1) which means
163 2: (R1, R0) = (1, 0) which means
164 3: (R1, R0) = (1, 1) which means
165 $ref: /schemas/types.yaml#/definit
166 enum: [0, 1, 2, 3]
167
168 mediatek,tdsel:
169 description:
170 An integer describing the steps
171 cycle when asserted (high pulse
172 are from 0 to 15.
173 $ref: /schemas/types.yaml#/definit
174
175 mediatek,rdsel:
176 description:
177 An integer describing the steps
178 when asserted (high pulse width
179 from 0 to 63.
180 $ref: /schemas/types.yaml#/definit
181
182 required:
183 - pinmux
184
185 additionalProperties: false
186
187 examples:
188 - |
189 #include <dt-bindings/interrupt-controller
190 #include <dt-bindings/interrupt-controller
191 #include <dt-bindings/pinctrl/mt8183-pinfu
192
193 soc {
194 #address-cells = <2>;
195 #size-cells = <2>;
196
197 pio: pinctrl@10005000 {
198 compatible = "mediatek,mt8183-pinctr
199 reg = <0 0x10005000 0 0x1000>,
200 <0 0x11f20000 0 0x1000>,
201 <0 0x11e80000 0 0x1000>,
202 <0 0x11e70000 0 0x1000>,
203 <0 0x11e90000 0 0x1000>,
204 <0 0x11d30000 0 0x1000>,
205 <0 0x11d20000 0 0x1000>,
206 <0 0x11c50000 0 0x1000>,
207 <0 0x11f30000 0 0x1000>,
208 <0 0x1000b000 0 0x1000>;
209 reg-names = "iocfg0", "iocfg1", "ioc
210 "iocfg3", "iocfg4", "iocfg5",
211 "iocfg6", "iocfg7", "iocfg8",
212 "eint";
213 gpio-controller;
214 #gpio-cells = <2>;
215 gpio-ranges = <&pio 0 0 192>;
216 interrupt-controller;
217 interrupts = <GIC_SPI 177 IRQ_TYPE_L
218 #interrupt-cells = <2>;
219
220 i2c0_pins_a: i2c0-pins {
221 pins1 {
222 pinmux = <PINMUX_GPIO48__FUNC_SC
223 <PINMUX_GPIO49__FUNC_SDA5>;
224 mediatek,pull-up-adv = <3>;
225 drive-strength-microamp = <1000>
226 };
227 };
228
229 i2c1_pins_a: i2c1-pins {
230 pins {
231 pinmux = <PINMUX_GPIO50__FUNC_SC
232 <PINMUX_GPIO51__FUNC_SDA3>;
233 mediatek,pull-down-adv = <2>;
234 };
235 };
236 };
237 };
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