1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/med 4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek MT8183 Pin Controller 7 title: MediaTek MT8183 Pin Controller
8 8
9 maintainers: 9 maintainers:
10 - Sean Wang <sean.wang@kernel.org> 10 - Sean Wang <sean.wang@kernel.org>
11 11
12 description: 12 description:
13 The MediaTek's MT8183 Pin controller is used 13 The MediaTek's MT8183 Pin controller is used to control SoC pins.
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 const: mediatek,mt8183-pinctrl 17 const: mediatek,mt8183-pinctrl
18 18
19 reg: 19 reg:
20 minItems: 10 20 minItems: 10
21 maxItems: 10 21 maxItems: 10
22 22
23 reg-names: 23 reg-names:
24 items: 24 items:
25 - const: iocfg0 25 - const: iocfg0
26 - const: iocfg1 26 - const: iocfg1
27 - const: iocfg2 27 - const: iocfg2
28 - const: iocfg3 28 - const: iocfg3
29 - const: iocfg4 29 - const: iocfg4
30 - const: iocfg5 30 - const: iocfg5
31 - const: iocfg6 31 - const: iocfg6
32 - const: iocfg7 32 - const: iocfg7
33 - const: iocfg8 33 - const: iocfg8
34 - const: eint 34 - const: eint
35 35
36 gpio-controller: true 36 gpio-controller: true
37 37
38 "#gpio-cells": 38 "#gpio-cells":
39 const: 2 39 const: 2
40 description: 40 description:
41 Number of cells in GPIO specifier. Since 41 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
42 the amount of cells must be specified as 42 the amount of cells must be specified as 2. See the below mentioned gpio
43 binding representation for description o 43 binding representation for description of particular cells.
44 44
45 gpio-ranges: 45 gpio-ranges:
46 minItems: 1 46 minItems: 1
47 maxItems: 5 47 maxItems: 5
48 description: 48 description:
49 GPIO valid number range. 49 GPIO valid number range.
50 50
51 interrupt-controller: true 51 interrupt-controller: true
52 52
53 interrupts: 53 interrupts:
54 maxItems: 1 54 maxItems: 1
55 55
56 "#interrupt-cells": 56 "#interrupt-cells":
57 const: 2 57 const: 2
58 58
59 allOf: 59 allOf:
60 - $ref: pinctrl.yaml# 60 - $ref: pinctrl.yaml#
61 61
62 required: 62 required:
63 - compatible 63 - compatible
64 - reg 64 - reg
65 - gpio-controller 65 - gpio-controller
66 - "#gpio-cells" 66 - "#gpio-cells"
67 - gpio-ranges 67 - gpio-ranges
68 68
69 patternProperties: 69 patternProperties:
70 '-pins(-[a-z]+)?$': 70 '-pins(-[a-z]+)?$':
71 type: object 71 type: object
72 additionalProperties: false 72 additionalProperties: false
73 patternProperties: 73 patternProperties:
74 '^pins': 74 '^pins':
75 type: object 75 type: object
76 additionalProperties: false 76 additionalProperties: false
77 description: 77 description:
78 A pinctrl node should contain at lea 78 A pinctrl node should contain at least one subnodes representing the
79 pinctrl groups available on the mach 79 pinctrl groups available on the machine. Each subnode will list the
80 pins it needs, and how they should b 80 pins it needs, and how they should be configured, with regard to muxer
81 configuration, pullups, drive streng 81 configuration, pullups, drive strength, input enable/disable and input
82 schmitt. 82 schmitt.
83 $ref: /schemas/pinctrl/pincfg-node.yam 83 $ref: /schemas/pinctrl/pincfg-node.yaml
84 84
85 properties: 85 properties:
86 pinmux: 86 pinmux:
87 description: 87 description:
88 Integer array, represents gpio p 88 Integer array, represents gpio pin number and mux setting.
89 Supported pin number and mux var 89 Supported pin number and mux varies for different SoCs, and are
90 defined as macros in <soc>-pinfu 90 defined as macros in <soc>-pinfunc.h directly.
91 91
92 bias-disable: true 92 bias-disable: true
93 93
94 bias-pull-up: true 94 bias-pull-up: true
95 95
96 bias-pull-down: true 96 bias-pull-down: true
97 97
98 input-enable: true 98 input-enable: true
99 99
100 input-disable: true 100 input-disable: true
101 101
102 output-low: true 102 output-low: true
103 103
104 output-high: true 104 output-high: true
105 105
106 input-schmitt-enable: true 106 input-schmitt-enable: true
107 107
108 input-schmitt-disable: true 108 input-schmitt-disable: true
109 109
110 drive-strength: 110 drive-strength:
111 enum: [2, 4, 6, 8, 10, 12, 14, 16] 111 enum: [2, 4, 6, 8, 10, 12, 14, 16]
112 112
113 drive-strength-microamp: 113 drive-strength-microamp:
114 enum: [125, 250, 500, 1000] 114 enum: [125, 250, 500, 1000]
115 115
116 mediatek,drive-strength-adv: 116 mediatek,drive-strength-adv:
117 deprecated: true 117 deprecated: true
118 description: | 118 description: |
119 DEPRECATED: Please use drive-str 119 DEPRECATED: Please use drive-strength-microamp instead.
120 Describe the specific driving se 120 Describe the specific driving setup property.
121 For I2C pins, the existing gener 121 For I2C pins, the existing generic driving setup can only support
122 2/4/6/8/10/12/14/16mA driving. B 122 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
123 can support 0.125/0.25/0.5/1mA a 123 can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
124 driving setup, the existing gene 124 driving setup, the existing generic setup will be disabled.
125 The specific driving setup is co 125 The specific driving setup is controlled by E1E0EN.
126 When E1=0/E0=0, the strength is 126 When E1=0/E0=0, the strength is 0.125mA.
127 When E1=0/E0=1, the strength is 127 When E1=0/E0=1, the strength is 0.25mA.
128 When E1=1/E0=0, the strength is 128 When E1=1/E0=0, the strength is 0.5mA.
129 When E1=1/E0=1, the strength is 129 When E1=1/E0=1, the strength is 1mA.
130 EN is used to enable or disable 130 EN is used to enable or disable the specific driving setup.
131 Valid arguments are described as 131 Valid arguments are described as below:
132 0: (E1, E0, EN) = (0, 0, 0) 132 0: (E1, E0, EN) = (0, 0, 0)
133 1: (E1, E0, EN) = (0, 0, 1) 133 1: (E1, E0, EN) = (0, 0, 1)
134 2: (E1, E0, EN) = (0, 1, 0) 134 2: (E1, E0, EN) = (0, 1, 0)
135 3: (E1, E0, EN) = (0, 1, 1) 135 3: (E1, E0, EN) = (0, 1, 1)
136 4: (E1, E0, EN) = (1, 0, 0) 136 4: (E1, E0, EN) = (1, 0, 0)
137 5: (E1, E0, EN) = (1, 0, 1) 137 5: (E1, E0, EN) = (1, 0, 1)
138 6: (E1, E0, EN) = (1, 1, 0) 138 6: (E1, E0, EN) = (1, 1, 0)
139 7: (E1, E0, EN) = (1, 1, 1) 139 7: (E1, E0, EN) = (1, 1, 1)
140 So the valid arguments are from 140 So the valid arguments are from 0 to 7.
141 $ref: /schemas/types.yaml#/definit 141 $ref: /schemas/types.yaml#/definitions/uint32
142 enum: [0, 1, 2, 3, 4, 5, 6, 7] 142 enum: [0, 1, 2, 3, 4, 5, 6, 7]
143 143
144 mediatek,pull-up-adv: 144 mediatek,pull-up-adv:
145 description: | 145 description: |
146 Pull up settings for 2 pull resi !! 146 Pull up setings for 2 pull resistors, R0 and R1. User can
147 configure those special pins. Va 147 configure those special pins. Valid arguments are described as
148 below: 148 below:
149 0: (R1, R0) = (0, 0) which means 149 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
150 1: (R1, R0) = (0, 1) which means 150 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
151 2: (R1, R0) = (1, 0) which means 151 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
152 3: (R1, R0) = (1, 1) which means 152 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
153 $ref: /schemas/types.yaml#/definit 153 $ref: /schemas/types.yaml#/definitions/uint32
154 enum: [0, 1, 2, 3] 154 enum: [0, 1, 2, 3]
155 155
156 mediatek,pull-down-adv: 156 mediatek,pull-down-adv:
157 description: | 157 description: |
158 Pull down settings for 2 pull re 158 Pull down settings for 2 pull resistors, R0 and R1. User can
159 configure those special pins. Va 159 configure those special pins. Valid arguments are described as
160 below: 160 below:
161 0: (R1, R0) = (0, 0) which means 161 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
162 1: (R1, R0) = (0, 1) which means 162 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
163 2: (R1, R0) = (1, 0) which means 163 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
164 3: (R1, R0) = (1, 1) which means 164 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
165 $ref: /schemas/types.yaml#/definit 165 $ref: /schemas/types.yaml#/definitions/uint32
166 enum: [0, 1, 2, 3] 166 enum: [0, 1, 2, 3]
167 167
168 mediatek,tdsel: 168 mediatek,tdsel:
169 description: 169 description:
170 An integer describing the steps 170 An integer describing the steps for output level shifter duty
171 cycle when asserted (high pulse 171 cycle when asserted (high pulse width adjustment). Valid arguments
172 are from 0 to 15. 172 are from 0 to 15.
173 $ref: /schemas/types.yaml#/definit 173 $ref: /schemas/types.yaml#/definitions/uint32
174 174
175 mediatek,rdsel: 175 mediatek,rdsel:
176 description: 176 description:
177 An integer describing the steps 177 An integer describing the steps for input level shifter duty cycle
178 when asserted (high pulse width 178 when asserted (high pulse width adjustment). Valid arguments are
179 from 0 to 63. 179 from 0 to 63.
180 $ref: /schemas/types.yaml#/definit 180 $ref: /schemas/types.yaml#/definitions/uint32
181 181
182 required: 182 required:
183 - pinmux 183 - pinmux
184 184
185 additionalProperties: false 185 additionalProperties: false
186 186
187 examples: 187 examples:
188 - | 188 - |
189 #include <dt-bindings/interrupt-controller 189 #include <dt-bindings/interrupt-controller/irq.h>
190 #include <dt-bindings/interrupt-controller 190 #include <dt-bindings/interrupt-controller/arm-gic.h>
191 #include <dt-bindings/pinctrl/mt8183-pinfu 191 #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
192 192
193 soc { 193 soc {
194 #address-cells = <2>; 194 #address-cells = <2>;
195 #size-cells = <2>; 195 #size-cells = <2>;
196 196
197 pio: pinctrl@10005000 { 197 pio: pinctrl@10005000 {
198 compatible = "mediatek,mt8183-pinctr 198 compatible = "mediatek,mt8183-pinctrl";
199 reg = <0 0x10005000 0 0x1000>, 199 reg = <0 0x10005000 0 0x1000>,
200 <0 0x11f20000 0 0x1000>, 200 <0 0x11f20000 0 0x1000>,
201 <0 0x11e80000 0 0x1000>, 201 <0 0x11e80000 0 0x1000>,
202 <0 0x11e70000 0 0x1000>, 202 <0 0x11e70000 0 0x1000>,
203 <0 0x11e90000 0 0x1000>, 203 <0 0x11e90000 0 0x1000>,
204 <0 0x11d30000 0 0x1000>, 204 <0 0x11d30000 0 0x1000>,
205 <0 0x11d20000 0 0x1000>, 205 <0 0x11d20000 0 0x1000>,
206 <0 0x11c50000 0 0x1000>, 206 <0 0x11c50000 0 0x1000>,
207 <0 0x11f30000 0 0x1000>, 207 <0 0x11f30000 0 0x1000>,
208 <0 0x1000b000 0 0x1000>; 208 <0 0x1000b000 0 0x1000>;
209 reg-names = "iocfg0", "iocfg1", "ioc 209 reg-names = "iocfg0", "iocfg1", "iocfg2",
210 "iocfg3", "iocfg4", "iocfg5", 210 "iocfg3", "iocfg4", "iocfg5",
211 "iocfg6", "iocfg7", "iocfg8", 211 "iocfg6", "iocfg7", "iocfg8",
212 "eint"; 212 "eint";
213 gpio-controller; 213 gpio-controller;
214 #gpio-cells = <2>; 214 #gpio-cells = <2>;
215 gpio-ranges = <&pio 0 0 192>; 215 gpio-ranges = <&pio 0 0 192>;
216 interrupt-controller; 216 interrupt-controller;
217 interrupts = <GIC_SPI 177 IRQ_TYPE_L 217 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
218 #interrupt-cells = <2>; 218 #interrupt-cells = <2>;
219 219
220 i2c0_pins_a: i2c0-pins { 220 i2c0_pins_a: i2c0-pins {
221 pins1 { 221 pins1 {
222 pinmux = <PINMUX_GPIO48__FUNC_SC 222 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
223 <PINMUX_GPIO49__FUNC_SDA5>; 223 <PINMUX_GPIO49__FUNC_SDA5>;
224 mediatek,pull-up-adv = <3>; 224 mediatek,pull-up-adv = <3>;
225 drive-strength-microamp = <1000> 225 drive-strength-microamp = <1000>;
226 }; 226 };
227 }; 227 };
228 228
229 i2c1_pins_a: i2c1-pins { 229 i2c1_pins_a: i2c1-pins {
230 pins { 230 pins {
231 pinmux = <PINMUX_GPIO50__FUNC_SC 231 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
232 <PINMUX_GPIO51__FUNC_SDA3>; 232 <PINMUX_GPIO51__FUNC_SDA3>;
233 mediatek,pull-down-adv = <2>; 233 mediatek,pull-down-adv = <2>;
234 }; 234 };
235 }; 235 };
236 }; 236 };
237 }; 237 };
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