1 # SPDX-License-Identifier: GPL-2.0-only OR BSD
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuv
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Nuvoton NPCM845 Pin Controller and GPIO
8
9 maintainers:
10 - Tomer Maimon <tmaimon77@gmail.com>
11
12 description:
13 The Nuvoton BMC NPCM8XX Pin Controller multi
14 the multiplexing block, Each pin supports GP
15 and multiple functions that directly connect
16 hardware blocks.
17
18 properties:
19 compatible:
20 const: nuvoton,npcm845-pinctrl
21
22 ranges:
23 maxItems: 1
24
25 '#address-cells':
26 const: 1
27
28 '#size-cells':
29 const: 1
30
31 nuvoton,sysgcr:
32 $ref: /schemas/types.yaml#/definitions/pha
33 description: a phandle to access GCR regis
34
35 patternProperties:
36 '^gpio@':
37 type: object
38 additionalProperties: false
39
40 description:
41 Eight GPIO banks that each contain 32 GP
42
43 properties:
44 gpio-controller: true
45
46 '#gpio-cells':
47 const: 2
48
49 reg:
50 maxItems: 1
51
52 interrupts:
53 maxItems: 1
54
55 gpio-ranges:
56 maxItems: 1
57
58 required:
59 - gpio-controller
60 - '#gpio-cells'
61 - reg
62 - interrupts
63 - gpio-ranges
64
65 '-mux$':
66 $ref: pinmux-node.yaml#
67
68 properties:
69 groups:
70 description:
71 One or more groups of pins to mux to
72 items:
73 enum: [ iox1, iox2, smb1d, smb2d, lk
74 smb5b, smb5c, lkgpo0, pspi,
75 smb16, smb17, smb18, smb19,
76 smb23b, smb4d, smb14, smb5,
77 spi0cs3, spi1cs0, spi1cs1, s
78 smb3b, bmcuart0a, uart1, jta
79 bmcuart0b, r1err, r1md, r1oe
80 fanin0, fanin1, fanin2, fani
81 fanin7, fanin8, fanin9, fani
82 fanin14, fanin15, pwm0, pwm1
83 r3rxer, ga20kbc, smb5d, lpc,
84 i3c2, i3c3, i3c4, i3c5, smb0
85 smb1b, smb8, smb9, smb10, sm
86 pwm6, pwm7, pwm8, pwm9, pwm1
87 mmcrst, clkout, serirq, scip
88 smb6d, smb7, smb7b, smb7c, s
89 spi3cs1, spi3quad, spi3cs2,
90 smb0den, smb0d, ddc, rg2mdio
91 spix, spixcs1, clkreq, hgpio
92 hgpio5, hgpio6, hgpio7, bu4,
93
94 function:
95 description:
96 The function that a group of pins is
97 enum: [ iox1, iox2, smb1d, smb2d, lkgp
98 smb5c, lkgpo0, pspi, jm1, jm2,
99 smb17, smb18, smb19, smb20, sm
100 smb14, smb5, smb4, smb3, spi0c
101 spi1cs1, spi1cs2, spi1cs3, spi
102 uart1, jtag2, bmcuart1, uart2,
103 r1oen, r2oen, rmii3, r3oen, sm
104 fanin3, fanin4, fanin5, fanin6
105 fanin11, fanin12, fanin13, fan
106 pwm3, r2, r2err, r2md, r3rxer,
107 ddr, i3c0, i3c1, i3c2, i3c3, i
108 smb2c, smb2b, smb1c, smb1b, sm
109 sd1pwr, pwm4, pwm5, pwm6, pwm7
110 mmc8, mmc, mmcwp, mmccd, mmcrs
111 smb6, smb6b, smb6c, smb6d, smb
112 faninx, r1, spi3, spi3cs1, spi
113 smb0b, smb0c, smb0den, smb0d,
114 smb12, smb13, spix, spixcs1, c
115 hgpio3, hgpio4, hgpio5, hgpio6
116 bu6, gpo187 ]
117
118 dependencies:
119 groups: [ function ]
120 function: [ groups ]
121
122 additionalProperties: false
123
124 '^pin':
125 $ref: pincfg-node.yaml#
126
127 properties:
128 pins:
129 description:
130 A list of pins to configure in certa
131 debouncing
132 items:
133 pattern: '^GPIO([0-9]|[0-9][0-9]|1[0
134
135 bias-disable: true
136
137 bias-pull-up: true
138
139 bias-pull-down: true
140
141 input-enable: true
142
143 output-low: true
144
145 output-high: true
146
147 drive-push-pull: true
148
149 drive-open-drain: true
150
151 input-debounce:
152 description:
153 Debouncing periods in microseconds,
154 bank found in the controller
155 minItems: 1
156 maxItems: 4
157
158 slew-rate:
159 description: |
160 0: Low rate
161 1: High rate
162 enum: [0, 1]
163
164 drive-strength:
165 enum: [ 0, 1, 2, 4, 8, 12 ]
166
167 additionalProperties: false
168
169 allOf:
170 - $ref: pinctrl.yaml#
171
172 required:
173 - compatible
174 - ranges
175 - '#address-cells'
176 - '#size-cells'
177 - nuvoton,sysgcr
178
179 additionalProperties: false
180
181 examples:
182 - |
183 #include <dt-bindings/interrupt-controller
184 #include <dt-bindings/gpio/gpio.h>
185
186 soc {
187 #address-cells = <2>;
188 #size-cells = <2>;
189
190 pinctrl: pinctrl@f0010000 {
191 compatible = "nuvoton,npcm845-pinctrl"
192 ranges = <0x0 0x0 0xf0010000 0x8000>;
193 #address-cells = <1>;
194 #size-cells = <1>;
195 nuvoton,sysgcr = <&gcr>;
196
197 gpio0: gpio@0 {
198 gpio-controller;
199 #gpio-cells = <2>;
200 reg = <0x0 0xb0>;
201 interrupts = <GIC_SPI 116 IRQ_TYPE_L
202 gpio-ranges = <&pinctrl 0 0 32>;
203 };
204
205 fanin0_pin: fanin0-mux {
206 groups = "fanin0";
207 function = "fanin0";
208 };
209
210 pin34_slew: pin34-slew {
211 pins = "GPIO34/I3C4_SDA";
212 bias-disable;
213 };
214 };
215 };
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