1 Device tree binding for NVIDIA Tegra XUSB pad 1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ============================================== 2 ========================================================
3 3
4 NOTE: It turns out that this binding isn't an <<
5 pad controller. While the description is good <<
6 required for PCIe and SATA, it lacks the flexi <<
7 needed for USB. For the new binding, see ../ph <<
8 The binding described in this file is deprecat <<
9 <<
10 The Tegra XUSB pad controller manages a set of 4 The Tegra XUSB pad controller manages a set of lanes, each of which can be
11 assigned to one out of a set of different pads 5 assigned to one out of a set of different pads. Some of these pads have an
12 associated PHY that must be powered up before 6 associated PHY that must be powered up before the pad can be used.
13 7
14 This document defines the device-specific bind 8 This document defines the device-specific binding for the XUSB pad controller.
15 9
16 Refer to pinctrl-bindings.txt in this director 10 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy 11 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
18 how to describe and reference PHYs in device t 12 how to describe and reference PHYs in device trees.
19 13
20 Required properties: 14 Required properties:
21 -------------------- 15 --------------------
22 - compatible: For Tegra124, must contain "nvid 16 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb 17 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> 18 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the 19 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry 20 - resets: Must contain an entry for each entry in reset-names.
27 See ../reset/reset.txt for details. 21 See ../reset/reset.txt for details.
28 - reset-names: Must include the following entr 22 - reset-names: Must include the following entries:
29 - padctl 23 - padctl
30 - #phy-cells: Should be 1. The specifier is th 24 - #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
31 See <dt-bindings/pinctrl/pinctrl-tegra-xusb. 25 See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.
32 26
33 Lane muxing: 27 Lane muxing:
34 ------------ 28 ------------
35 29
36 Child nodes contain the pinmux configurations 30 Child nodes contain the pinmux configurations following the conventions from
37 the pinctrl-bindings.txt document. Typically a 31 the pinctrl-bindings.txt document. Typically a single, static configuration is
38 given and applied at boot time. 32 given and applied at boot time.
39 33
40 Each subnode describes groups of lanes along w 34 Each subnode describes groups of lanes along with parameters and pads that
41 they should be assigned to. The name of these 35 they should be assigned to. The name of these subnodes is not important. All
42 subnodes should be parsed solely based on thei 36 subnodes should be parsed solely based on their content.
43 37
44 Each subnode only applies the parameters that 38 Each subnode only applies the parameters that are explicitly listed. In other
45 words, if a subnode that lists a function but 39 words, if a subnode that lists a function but no pin configuration parameters
46 implies no information about any pin configura 40 implies no information about any pin configuration parameters. Similarly, a
47 subnode that describes only an IDDQ parameter 41 subnode that describes only an IDDQ parameter implies no information about
48 what function the pins are assigned to. For th 42 what function the pins are assigned to. For this reason even seemingly boolean
49 values are actually tristates in this binding: 43 values are actually tristates in this binding: unspecified, off or on.
50 Unspecified is represented as an absent proper 44 Unspecified is represented as an absent property, and off/on are represented
51 as integer values 0 and 1. 45 as integer values 0 and 1.
52 46
53 Required properties: 47 Required properties:
54 - nvidia,lanes: An array of strings. Each stri 48 - nvidia,lanes: An array of strings. Each string is the name of a lane.
55 49
56 Optional properties: 50 Optional properties:
57 - nvidia,function: A string that is the name o 51 - nvidia,function: A string that is the name of the function (pad) that the
58 pin or group should be assigned to. Valid va 52 pin or group should be assigned to. Valid values for function names are
59 listed below. 53 listed below.
60 - nvidia,iddq: Enables IDDQ mode of the lane. 54 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
61 55
62 Note that not all of these properties are vali 56 Note that not all of these properties are valid for all lanes. Lanes can be
63 divided into three groups: 57 divided into three groups:
64 58
65 - otg-0, otg-1, otg-2: 59 - otg-0, otg-1, otg-2:
66 60
67 Valid functions for this group are: "snps" 61 Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
68 62
69 The nvidia,iddq property does not apply to 63 The nvidia,iddq property does not apply to this group.
70 64
71 - ulpi-0, hsic-0, hsic-1: 65 - ulpi-0, hsic-0, hsic-1:
72 66
73 Valid functions for this group are: "snps" 67 Valid functions for this group are: "snps", "xusb".
74 68
75 The nvidia,iddq property does not apply to 69 The nvidia,iddq property does not apply to this group.
76 70
77 - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sa 71 - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
78 72
79 Valid functions for this group are: "pcie" 73 Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
80 74
81 75
82 Example: 76 Example:
83 ======== 77 ========
84 78
85 SoC file extract: 79 SoC file extract:
86 ----------------- 80 -----------------
87 81
88 padctl@7009f000 { !! 82 padctl@0,7009f000 {
89 compatible = "nvidia,tegra124- 83 compatible = "nvidia,tegra124-xusb-padctl";
90 reg = <0x0 0x7009f000 0x0 0x10 84 reg = <0x0 0x7009f000 0x0 0x1000>;
91 resets = <&tegra_car 142>; 85 resets = <&tegra_car 142>;
92 reset-names = "padctl"; 86 reset-names = "padctl";
93 87
94 #phy-cells = <1>; 88 #phy-cells = <1>;
95 }; 89 };
96 90
97 Board file extract: 91 Board file extract:
98 ------------------- 92 -------------------
99 93
100 pcie-controller@1003000 { !! 94 pcie-controller@0,01003000 {
101 ... 95 ...
102 96
103 phys = <&padctl 0>; 97 phys = <&padctl 0>;
104 phy-names = "pcie"; 98 phy-names = "pcie";
105 99
106 ... 100 ...
107 }; 101 };
108 102
109 ... 103 ...
110 104
111 padctl: padctl@7009f000 { !! 105 padctl: padctl@0,7009f000 {
112 pinctrl-0 = <&padctl_default>; 106 pinctrl-0 = <&padctl_default>;
113 pinctrl-names = "default"; 107 pinctrl-names = "default";
114 108
115 padctl_default: pinmux { 109 padctl_default: pinmux {
116 usb3 { 110 usb3 {
117 nvidia,lanes = 111 nvidia,lanes = "pcie-0", "pcie-1";
118 nvidia,functio 112 nvidia,function = "usb3";
119 nvidia,iddq = 113 nvidia,iddq = <0>;
120 }; 114 };
121 115
122 pcie { 116 pcie {
123 nvidia,lanes = 117 nvidia,lanes = "pcie-2", "pcie-3",
124 118 "pcie-4";
125 nvidia,functio 119 nvidia,function = "pcie";
126 nvidia,iddq = 120 nvidia,iddq = <0>;
127 }; 121 };
128 122
129 sata { 123 sata {
130 nvidia,lanes = 124 nvidia,lanes = "sata-0";
131 nvidia,functio 125 nvidia,function = "sata";
132 nvidia,iddq = 126 nvidia,iddq = <0>;
133 }; 127 };
134 }; 128 };
135 }; 129 };
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