1 Device tree binding for NVIDIA Tegra XUSB pad 1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ============================================== 2 ========================================================
3 3
4 NOTE: It turns out that this binding isn't an 4 NOTE: It turns out that this binding isn't an accurate description of the XUSB
5 pad controller. While the description is good 5 pad controller. While the description is good enough for the functional subset
6 required for PCIe and SATA, it lacks the flexi 6 required for PCIe and SATA, it lacks the flexibility to represent the features
7 needed for USB. For the new binding, see ../ph 7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
8 The binding described in this file is deprecat 8 The binding described in this file is deprecated and should not be used.
9 9
10 The Tegra XUSB pad controller manages a set of 10 The Tegra XUSB pad controller manages a set of lanes, each of which can be
11 assigned to one out of a set of different pads 11 assigned to one out of a set of different pads. Some of these pads have an
12 associated PHY that must be powered up before 12 associated PHY that must be powered up before the pad can be used.
13 13
14 This document defines the device-specific bind 14 This document defines the device-specific binding for the XUSB pad controller.
15 15
16 Refer to pinctrl-bindings.txt in this director 16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy 17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
18 how to describe and reference PHYs in device t 18 how to describe and reference PHYs in device trees.
19 19
20 Required properties: 20 Required properties:
21 -------------------- 21 --------------------
22 - compatible: For Tegra124, must contain "nvid 22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb 23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> 24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the 25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry 26 - resets: Must contain an entry for each entry in reset-names.
27 See ../reset/reset.txt for details. 27 See ../reset/reset.txt for details.
28 - reset-names: Must include the following entr 28 - reset-names: Must include the following entries:
29 - padctl 29 - padctl
30 - #phy-cells: Should be 1. The specifier is th 30 - #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
31 See <dt-bindings/pinctrl/pinctrl-tegra-xusb. 31 See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.
32 32
33 Lane muxing: 33 Lane muxing:
34 ------------ 34 ------------
35 35
36 Child nodes contain the pinmux configurations 36 Child nodes contain the pinmux configurations following the conventions from
37 the pinctrl-bindings.txt document. Typically a 37 the pinctrl-bindings.txt document. Typically a single, static configuration is
38 given and applied at boot time. 38 given and applied at boot time.
39 39
40 Each subnode describes groups of lanes along w 40 Each subnode describes groups of lanes along with parameters and pads that
41 they should be assigned to. The name of these 41 they should be assigned to. The name of these subnodes is not important. All
42 subnodes should be parsed solely based on thei 42 subnodes should be parsed solely based on their content.
43 43
44 Each subnode only applies the parameters that 44 Each subnode only applies the parameters that are explicitly listed. In other
45 words, if a subnode that lists a function but 45 words, if a subnode that lists a function but no pin configuration parameters
46 implies no information about any pin configura 46 implies no information about any pin configuration parameters. Similarly, a
47 subnode that describes only an IDDQ parameter 47 subnode that describes only an IDDQ parameter implies no information about
48 what function the pins are assigned to. For th 48 what function the pins are assigned to. For this reason even seemingly boolean
49 values are actually tristates in this binding: 49 values are actually tristates in this binding: unspecified, off or on.
50 Unspecified is represented as an absent proper 50 Unspecified is represented as an absent property, and off/on are represented
51 as integer values 0 and 1. 51 as integer values 0 and 1.
52 52
53 Required properties: 53 Required properties:
54 - nvidia,lanes: An array of strings. Each stri 54 - nvidia,lanes: An array of strings. Each string is the name of a lane.
55 55
56 Optional properties: 56 Optional properties:
57 - nvidia,function: A string that is the name o 57 - nvidia,function: A string that is the name of the function (pad) that the
58 pin or group should be assigned to. Valid va 58 pin or group should be assigned to. Valid values for function names are
59 listed below. 59 listed below.
60 - nvidia,iddq: Enables IDDQ mode of the lane. 60 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
61 61
62 Note that not all of these properties are vali 62 Note that not all of these properties are valid for all lanes. Lanes can be
63 divided into three groups: 63 divided into three groups:
64 64
65 - otg-0, otg-1, otg-2: 65 - otg-0, otg-1, otg-2:
66 66
67 Valid functions for this group are: "snps" 67 Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
68 68
69 The nvidia,iddq property does not apply to 69 The nvidia,iddq property does not apply to this group.
70 70
71 - ulpi-0, hsic-0, hsic-1: 71 - ulpi-0, hsic-0, hsic-1:
72 72
73 Valid functions for this group are: "snps" 73 Valid functions for this group are: "snps", "xusb".
74 74
75 The nvidia,iddq property does not apply to 75 The nvidia,iddq property does not apply to this group.
76 76
77 - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sa 77 - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
78 78
79 Valid functions for this group are: "pcie" 79 Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
80 80
81 81
82 Example: 82 Example:
83 ======== 83 ========
84 84
85 SoC file extract: 85 SoC file extract:
86 ----------------- 86 -----------------
87 87
88 padctl@7009f000 { 88 padctl@7009f000 {
89 compatible = "nvidia,tegra124- 89 compatible = "nvidia,tegra124-xusb-padctl";
90 reg = <0x0 0x7009f000 0x0 0x10 90 reg = <0x0 0x7009f000 0x0 0x1000>;
91 resets = <&tegra_car 142>; 91 resets = <&tegra_car 142>;
92 reset-names = "padctl"; 92 reset-names = "padctl";
93 93
94 #phy-cells = <1>; 94 #phy-cells = <1>;
95 }; 95 };
96 96
97 Board file extract: 97 Board file extract:
98 ------------------- 98 -------------------
99 99
100 pcie-controller@1003000 { 100 pcie-controller@1003000 {
101 ... 101 ...
102 102
103 phys = <&padctl 0>; 103 phys = <&padctl 0>;
104 phy-names = "pcie"; 104 phy-names = "pcie";
105 105
106 ... 106 ...
107 }; 107 };
108 108
109 ... 109 ...
110 110
111 padctl: padctl@7009f000 { 111 padctl: padctl@7009f000 {
112 pinctrl-0 = <&padctl_default>; 112 pinctrl-0 = <&padctl_default>;
113 pinctrl-names = "default"; 113 pinctrl-names = "default";
114 114
115 padctl_default: pinmux { 115 padctl_default: pinmux {
116 usb3 { 116 usb3 {
117 nvidia,lanes = 117 nvidia,lanes = "pcie-0", "pcie-1";
118 nvidia,functio 118 nvidia,function = "usb3";
119 nvidia,iddq = 119 nvidia,iddq = <0>;
120 }; 120 };
121 121
122 pcie { 122 pcie {
123 nvidia,lanes = 123 nvidia,lanes = "pcie-2", "pcie-3",
124 124 "pcie-4";
125 nvidia,functio 125 nvidia,function = "pcie";
126 nvidia,iddq = 126 nvidia,iddq = <0>;
127 }; 127 };
128 128
129 sata { 129 sata {
130 nvidia,lanes = 130 nvidia,lanes = "sata-0";
131 nvidia,functio 131 nvidia,function = "sata";
132 nvidia,iddq = 132 nvidia,iddq = <0>;
133 }; 133 };
134 }; 134 };
135 }; 135 };
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