1 Device tree binding for NVIDIA Tegra XUSB pad
2 ==============================================
3
4 NOTE: It turns out that this binding isn't an
5 pad controller. While the description is good
6 required for PCIe and SATA, it lacks the flexi
7 needed for USB. For the new binding, see ../ph
8 The binding described in this file is deprecat
9
10 The Tegra XUSB pad controller manages a set of
11 assigned to one out of a set of different pads
12 associated PHY that must be powered up before
13
14 This document defines the device-specific bind
15
16 Refer to pinctrl-bindings.txt in this director
17 pin controller device tree bindings and ../phy
18 how to describe and reference PHYs in device t
19
20 Required properties:
21 --------------------
22 - compatible: For Tegra124, must contain "nvid
23 Otherwise, must contain '"nvidia,<chip>-xusb
24 "nvidia-tegra124-xusb-padctl"', where <chip>
25 - reg: Physical base address and length of the
26 - resets: Must contain an entry for each entry
27 See ../reset/reset.txt for details.
28 - reset-names: Must include the following entr
29 - padctl
30 - #phy-cells: Should be 1. The specifier is th
31 See <dt-bindings/pinctrl/pinctrl-tegra-xusb.
32
33 Lane muxing:
34 ------------
35
36 Child nodes contain the pinmux configurations
37 the pinctrl-bindings.txt document. Typically a
38 given and applied at boot time.
39
40 Each subnode describes groups of lanes along w
41 they should be assigned to. The name of these
42 subnodes should be parsed solely based on thei
43
44 Each subnode only applies the parameters that
45 words, if a subnode that lists a function but
46 implies no information about any pin configura
47 subnode that describes only an IDDQ parameter
48 what function the pins are assigned to. For th
49 values are actually tristates in this binding:
50 Unspecified is represented as an absent proper
51 as integer values 0 and 1.
52
53 Required properties:
54 - nvidia,lanes: An array of strings. Each stri
55
56 Optional properties:
57 - nvidia,function: A string that is the name o
58 pin or group should be assigned to. Valid va
59 listed below.
60 - nvidia,iddq: Enables IDDQ mode of the lane.
61
62 Note that not all of these properties are vali
63 divided into three groups:
64
65 - otg-0, otg-1, otg-2:
66
67 Valid functions for this group are: "snps"
68
69 The nvidia,iddq property does not apply to
70
71 - ulpi-0, hsic-0, hsic-1:
72
73 Valid functions for this group are: "snps"
74
75 The nvidia,iddq property does not apply to
76
77 - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sa
78
79 Valid functions for this group are: "pcie"
80
81
82 Example:
83 ========
84
85 SoC file extract:
86 -----------------
87
88 padctl@7009f000 {
89 compatible = "nvidia,tegra124-
90 reg = <0x0 0x7009f000 0x0 0x10
91 resets = <&tegra_car 142>;
92 reset-names = "padctl";
93
94 #phy-cells = <1>;
95 };
96
97 Board file extract:
98 -------------------
99
100 pcie-controller@1003000 {
101 ...
102
103 phys = <&padctl 0>;
104 phy-names = "pcie";
105
106 ...
107 };
108
109 ...
110
111 padctl: padctl@7009f000 {
112 pinctrl-0 = <&padctl_default>;
113 pinctrl-names = "default";
114
115 padctl_default: pinmux {
116 usb3 {
117 nvidia,lanes =
118 nvidia,functio
119 nvidia,iddq =
120 };
121
122 pcie {
123 nvidia,lanes =
124
125 nvidia,functio
126 nvidia,iddq =
127 };
128
129 sata {
130 nvidia,lanes =
131 nvidia,functio
132 nvidia,iddq =
133 };
134 };
135 };
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