1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm IPQ5018 TLMM pin controller 7 title: Qualcomm IPQ5018 TLMM pin controller
8 8
9 maintainers: 9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org> 10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@li 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12 12
13 description: 13 description:
14 Top Level Mode Multiplexer pin controller in 14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 const: qcom,ipq5018-tlmm 18 const: qcom,ipq5018-tlmm
19 19
20 reg: 20 reg:
21 maxItems: 1 21 maxItems: 1
22 22
23 interrupts: 23 interrupts:
24 maxItems: 1 24 maxItems: 1
25 25
26 gpio-reserved-ranges: 26 gpio-reserved-ranges:
27 minItems: 1 27 minItems: 1
28 maxItems: 24 28 maxItems: 24
29 29
30 gpio-line-names: 30 gpio-line-names:
31 maxItems: 47 31 maxItems: 47
32 32
33 patternProperties: 33 patternProperties:
34 "-state$": 34 "-state$":
35 oneOf: 35 oneOf:
36 - $ref: "#/$defs/qcom-ipq5018-tlmm-state 36 - $ref: "#/$defs/qcom-ipq5018-tlmm-state"
37 - patternProperties: 37 - patternProperties:
38 "-pins$": 38 "-pins$":
39 $ref: "#/$defs/qcom-ipq5018-tlmm-s 39 $ref: "#/$defs/qcom-ipq5018-tlmm-state"
40 additionalProperties: false 40 additionalProperties: false
41 41
42 $defs: 42 $defs:
43 qcom-ipq5018-tlmm-state: 43 qcom-ipq5018-tlmm-state:
44 type: object 44 type: object
45 description: 45 description:
46 Pinctrl node's client devices use subnod 46 Pinctrl node's client devices use subnodes for desired pin configuration.
47 Client device subnodes use below standar 47 Client device subnodes use below standard properties.
48 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tl 48 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
49 unevaluatedProperties: false 49 unevaluatedProperties: false
50 50
51 properties: 51 properties:
52 pins: 52 pins:
53 description: 53 description:
54 List of gpio pins affected by the pr 54 List of gpio pins affected by the properties specified in this
55 subnode. 55 subnode.
56 items: 56 items:
57 pattern: "^gpio([0-9]|[1-3][0-9]|4[0 57 pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
58 minItems: 1 58 minItems: 1
59 maxItems: 8 59 maxItems: 8
60 60
61 function: 61 function:
62 description: 62 description:
63 Specify the alternative function to 63 Specify the alternative function to be configured for the specified
64 pins. 64 pins.
65 65
66 enum: [ atest_char, audio_pdm0, audio_ 66 enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
67 audio_rxfsync, audio_rxmclk, a 67 audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
68 audio_txfsync, audio_txmclk, b 68 audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
69 blsp0_uart1, blsp1_i2c0, blsp1 69 blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
70 blsp1_uart0, blsp1_uart1, blsp 70 blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
71 blsp2_spi, blsp2_spi0, blsp2_s 71 blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
72 cri_trng0, cri_trng1, cxc_clk, 72 cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
73 gcc_plltest, gcc_tlmm, gpio, l 73 gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
74 pcie0_clk, pcie0_wake, pcie1_c 74 pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
75 prng_rosc, pwm0, pwm1, pwm2, p 75 prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
76 qdss_cti_trig_in_a1, qdss_cti_ 76 qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
77 qdss_cti_trig_out_a0, qdss_cti 77 qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
78 qdss_cti_trig_out_b0, qdss_cti 78 qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
79 qdss_traceclk_b, qdss_tracectl 79 qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
80 qdss_tracedata_a, qdss_traceda 80 qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
81 qspi_data, reset_out, sdc1_clk 81 qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
82 wci_rxd, wsa_swrm, wsi_clk3, w 82 wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
83 83
84 required: 84 required:
85 - pins 85 - pins
86 86
87 required: 87 required:
88 - compatible 88 - compatible
89 - reg 89 - reg
90 90
91 allOf: 91 allOf:
92 - $ref: /schemas/pinctrl/qcom,tlmm-common.ya 92 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
93 93
94 unevaluatedProperties: false 94 unevaluatedProperties: false
95 95
96 examples: 96 examples:
97 - | 97 - |
98 #include <dt-bindings/interrupt-controller 98 #include <dt-bindings/interrupt-controller/arm-gic.h>
99 tlmm: pinctrl@1000000 { 99 tlmm: pinctrl@1000000 {
100 compatible = "qcom,ipq5018-tlmm"; 100 compatible = "qcom,ipq5018-tlmm";
101 reg = <0x01000000 0x300000>; 101 reg = <0x01000000 0x300000>;
102 gpio-controller; 102 gpio-controller;
103 #gpio-cells = <2>; 103 #gpio-cells = <2>;
104 gpio-ranges = <&tlmm 0 0 47>; 104 gpio-ranges = <&tlmm 0 0 47>;
105 interrupt-controller; 105 interrupt-controller;
106 #interrupt-cells = <2>; 106 #interrupt-cells = <2>;
107 interrupts = <GIC_SPI 208 IRQ_TYPE_LEV 107 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
108 108
109 uart-w-state { 109 uart-w-state {
110 rx-pins { 110 rx-pins {
111 pins = "gpio33"; 111 pins = "gpio33";
112 function = "blsp1_uart1"; 112 function = "blsp1_uart1";
113 bias-pull-down; 113 bias-pull-down;
114 }; 114 };
115 115
116 tx-pins { 116 tx-pins {
117 pins = "gpio34"; 117 pins = "gpio34";
118 function = "blsp1_uart1"; 118 function = "blsp1_uart1";
119 bias-pull-down; 119 bias-pull-down;
120 }; 120 };
121 }; 121 };
122 }; 122 };
123 ... 123 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.