1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm IPQ5018 TLMM pin controller 7 title: Qualcomm IPQ5018 TLMM pin controller
8 8
9 maintainers: 9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org> 10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@li 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12 12
13 description: 13 description:
14 Top Level Mode Multiplexer pin controller in 14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 const: qcom,ipq5018-tlmm 18 const: qcom,ipq5018-tlmm
19 19
20 reg: 20 reg:
21 maxItems: 1 21 maxItems: 1
22 22
23 interrupts: 23 interrupts:
24 maxItems: 1 24 maxItems: 1
25 25
>> 26 interrupt-controller: true
>> 27 "#interrupt-cells": true
>> 28 gpio-controller: true
>> 29 "#gpio-cells": true
>> 30 gpio-ranges: true
>> 31 wakeup-parent: true
>> 32
26 gpio-reserved-ranges: 33 gpio-reserved-ranges:
27 minItems: 1 34 minItems: 1
28 maxItems: 24 35 maxItems: 24
29 36
30 gpio-line-names: 37 gpio-line-names:
31 maxItems: 47 38 maxItems: 47
32 39
33 patternProperties: 40 patternProperties:
34 "-state$": 41 "-state$":
35 oneOf: 42 oneOf:
36 - $ref: "#/$defs/qcom-ipq5018-tlmm-state 43 - $ref: "#/$defs/qcom-ipq5018-tlmm-state"
37 - patternProperties: 44 - patternProperties:
38 "-pins$": 45 "-pins$":
39 $ref: "#/$defs/qcom-ipq5018-tlmm-s 46 $ref: "#/$defs/qcom-ipq5018-tlmm-state"
40 additionalProperties: false 47 additionalProperties: false
41 48
42 $defs: 49 $defs:
43 qcom-ipq5018-tlmm-state: 50 qcom-ipq5018-tlmm-state:
44 type: object 51 type: object
45 description: 52 description:
46 Pinctrl node's client devices use subnod 53 Pinctrl node's client devices use subnodes for desired pin configuration.
47 Client device subnodes use below standar 54 Client device subnodes use below standard properties.
48 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tl 55 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
49 unevaluatedProperties: false 56 unevaluatedProperties: false
50 57
51 properties: 58 properties:
52 pins: 59 pins:
53 description: 60 description:
54 List of gpio pins affected by the pr 61 List of gpio pins affected by the properties specified in this
55 subnode. 62 subnode.
56 items: 63 items:
57 pattern: "^gpio([0-9]|[1-3][0-9]|4[0 64 pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
58 minItems: 1 65 minItems: 1
59 maxItems: 8 66 maxItems: 8
60 67
61 function: 68 function:
62 description: 69 description:
63 Specify the alternative function to 70 Specify the alternative function to be configured for the specified
64 pins. 71 pins.
65 72
66 enum: [ atest_char, audio_pdm0, audio_ 73 enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
67 audio_rxfsync, audio_rxmclk, a 74 audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
68 audio_txfsync, audio_txmclk, b 75 audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
69 blsp0_uart1, blsp1_i2c0, blsp1 76 blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
70 blsp1_uart0, blsp1_uart1, blsp 77 blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
71 blsp2_spi, blsp2_spi0, blsp2_s 78 blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
72 cri_trng0, cri_trng1, cxc_clk, 79 cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
73 gcc_plltest, gcc_tlmm, gpio, l 80 gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
74 pcie0_clk, pcie0_wake, pcie1_c 81 pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
75 prng_rosc, pwm0, pwm1, pwm2, p 82 prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
76 qdss_cti_trig_in_a1, qdss_cti_ 83 qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
77 qdss_cti_trig_out_a0, qdss_cti 84 qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
78 qdss_cti_trig_out_b0, qdss_cti 85 qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
79 qdss_traceclk_b, qdss_tracectl 86 qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
80 qdss_tracedata_a, qdss_traceda 87 qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
81 qspi_data, reset_out, sdc1_clk 88 qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
82 wci_rxd, wsa_swrm, wsi_clk3, w 89 wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
83 90
84 required: 91 required:
85 - pins 92 - pins
86 93
87 required: 94 required:
88 - compatible 95 - compatible
89 - reg 96 - reg
90 97
91 allOf: !! 98 additionalProperties: false
92 - $ref: /schemas/pinctrl/qcom,tlmm-common.ya <<
93 <<
94 unevaluatedProperties: false <<
95 99
96 examples: 100 examples:
97 - | 101 - |
98 #include <dt-bindings/interrupt-controller 102 #include <dt-bindings/interrupt-controller/arm-gic.h>
99 tlmm: pinctrl@1000000 { 103 tlmm: pinctrl@1000000 {
100 compatible = "qcom,ipq5018-tlmm"; 104 compatible = "qcom,ipq5018-tlmm";
101 reg = <0x01000000 0x300000>; 105 reg = <0x01000000 0x300000>;
102 gpio-controller; 106 gpio-controller;
103 #gpio-cells = <2>; 107 #gpio-cells = <2>;
104 gpio-ranges = <&tlmm 0 0 47>; 108 gpio-ranges = <&tlmm 0 0 47>;
105 interrupt-controller; 109 interrupt-controller;
106 #interrupt-cells = <2>; 110 #interrupt-cells = <2>;
107 interrupts = <GIC_SPI 208 IRQ_TYPE_LEV 111 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
108 112
109 uart-w-state { 113 uart-w-state {
110 rx-pins { 114 rx-pins {
111 pins = "gpio33"; 115 pins = "gpio33";
112 function = "blsp1_uart1"; 116 function = "blsp1_uart1";
113 bias-pull-down; 117 bias-pull-down;
114 }; 118 };
115 119
116 tx-pins { 120 tx-pins {
117 pins = "gpio34"; 121 pins = "gpio34";
118 function = "blsp1_uart1"; 122 function = "blsp1_uart1";
119 bias-pull-down; 123 bias-pull-down;
120 }; 124 };
121 }; 125 };
122 }; 126 };
123 ... 127 ...
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