1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SC8280XP SoC LPASS LPI TLMM !! 7 title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
>> 8 Low Power Island (LPI) TLMM block
8 9
9 maintainers: 10 maintainers:
10 - Srinivas Kandagatla <srinivas.kandagatla@li 11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 12
12 description: !! 13 description: |
13 Top Level Mode Multiplexer pin controller in !! 14 This binding describes the Top Level Mode Multiplexer block found in the
14 (LPASS) Low Power Island (LPI) of Qualcomm S !! 15 LPASS LPI IP on most Qualcomm SoCs
15 16
16 properties: 17 properties:
17 compatible: 18 compatible:
18 const: qcom,sc8280xp-lpass-lpi-pinctrl 19 const: qcom,sc8280xp-lpass-lpi-pinctrl
19 20
20 reg: 21 reg:
21 items: 22 items:
22 - description: LPASS LPI TLMM Control an 23 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers !! 24 - description: LPASS LPI pins SLEW registers
24 25
25 clocks: 26 clocks:
26 items: 27 items:
27 - description: LPASS Core voting clock 28 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock 29 - description: LPASS Audio voting clock
29 30
30 clock-names: 31 clock-names:
31 items: 32 items:
32 - const: core 33 - const: core
33 - const: audio 34 - const: audio
34 35
35 patternProperties: !! 36 gpio-controller: true
36 "-state$": !! 37
37 oneOf: !! 38 '#gpio-cells':
38 - $ref: "#/$defs/qcom-sc8280xp-lpass-sta !! 39 description: Specifying the pin number and flags, as defined in
39 - patternProperties: !! 40 include/dt-bindings/gpio/gpio.h
40 "-pins$": !! 41 const: 2
41 $ref: "#/$defs/qcom-sc8280xp-lpass <<
42 additionalProperties: false <<
43 42
44 $defs: !! 43 gpio-ranges:
45 qcom-sc8280xp-lpass-state: !! 44 maxItems: 1
>> 45
>> 46 #PIN CONFIGURATION NODES
>> 47 patternProperties:
>> 48 '-pins$':
46 type: object 49 type: object
47 description: 50 description:
48 Pinctrl node's client devices use subnod 51 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standar 52 Client device subnodes use below standard properties.
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qc !! 53 $ref: /schemas/pinctrl/pincfg-node.yaml
51 unevaluatedProperties: false <<
52 54
53 properties: 55 properties:
54 pins: 56 pins:
55 description: 57 description:
56 List of gpio pins affected by the pr 58 List of gpio pins affected by the properties specified in this
57 subnode. 59 subnode.
58 items: 60 items:
59 pattern: "^gpio([0-9]|1[0-8])$" !! 61 pattern: "^gpio([0-1]|1[0-8]])$"
60 62
61 function: 63 function:
62 enum: [ swr_tx_clk, swr_tx_data, swr_r 64 enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
63 dmic1_clk, dmic1_data, dmic2_c 65 dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
64 dmic4_data, i2s2_clk, i2s2_ws, 66 dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
65 qua_mi2s_sclk, qua_mi2s_ws, qu 67 qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
66 i2s1_data, wsa_swr_clk, wsa_sw 68 i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
67 wsa2_swr_data, i2s2_data, i2s3 69 wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
68 ext_mclk1_c, ext_mclk1_b, ext_ 70 ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
69 description: 71 description:
70 Specify the alternative function to 72 Specify the alternative function to be configured for the specified
71 pins. 73 pins.
72 74
>> 75 drive-strength:
>> 76 enum: [2, 4, 6, 8, 10, 12, 14, 16]
>> 77 default: 2
>> 78 description:
>> 79 Selects the drive strength for the specified pins, in mA.
>> 80
>> 81 slew-rate:
>> 82 enum: [0, 1, 2, 3]
>> 83 default: 0
>> 84 description: |
>> 85 0: No adjustments
>> 86 1: Higher Slew rate (faster edges)
>> 87 2: Lower Slew rate (slower edges)
>> 88 3: Reserved (No adjustments)
>> 89
>> 90 bias-pull-down: true
>> 91
>> 92 bias-pull-up: true
>> 93
>> 94 bias-disable: true
>> 95
>> 96 output-high: true
>> 97
>> 98 output-low: true
>> 99
>> 100 required:
>> 101 - pins
>> 102 - function
>> 103
>> 104 additionalProperties: false
>> 105
73 allOf: 106 allOf:
74 - $ref: qcom,lpass-lpi-common.yaml# !! 107 - $ref: pinctrl.yaml#
75 108
76 required: 109 required:
77 - compatible 110 - compatible
78 - reg 111 - reg
79 - clocks 112 - clocks
80 - clock-names 113 - clock-names
>> 114 - gpio-controller
>> 115 - '#gpio-cells'
>> 116 - gpio-ranges
81 117
82 unevaluatedProperties: false !! 118 additionalProperties: false
83 119
84 examples: 120 examples:
85 - | 121 - |
86 #include <dt-bindings/sound/qcom,q6afe.h> 122 #include <dt-bindings/sound/qcom,q6afe.h>
87 pinctrl@33c0000 { 123 pinctrl@33c0000 {
88 compatible = "qcom,sc8280xp-lpass-lpi- 124 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
89 reg = <0x33c0000 0x20000>, 125 reg = <0x33c0000 0x20000>,
90 <0x3550000 0x10000>; 126 <0x3550000 0x10000>;
91 clocks = <&q6afecc LPASS_HW_MACRO_VOTE 127 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
92 <&q6afecc LPASS_HW_DCODEC_VOT 128 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
93 clock-names = "core", "audio"; 129 clock-names = "core", "audio";
94 gpio-controller; 130 gpio-controller;
95 #gpio-cells = <2>; 131 #gpio-cells = <2>;
96 gpio-ranges = <&lpi_tlmm 0 0 19>; !! 132 gpio-ranges = <&lpi_tlmm 0 0 18>;
97 <<
98 dmic01-state { <<
99 dmic01-clk-pins { <<
100 pins = "gpio16"; <<
101 function = "dmic1_clk"; <<
102 }; <<
103 <<
104 dmic01-clk-sleep-pins { <<
105 pins = "gpio16"; <<
106 function = "dmic1_clk"; <<
107 }; <<
108 }; <<
109 <<
110 tx-swr-data-sleep-state { <<
111 pins = "gpio0", "gpio1"; <<
112 function = "swr_tx_data"; <<
113 }; <<
114 }; 133 };
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