1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SC8280XP SoC LPASS LPI TLMM 7 title: Qualcomm SC8280XP SoC LPASS LPI TLMM
8 8
9 maintainers: 9 maintainers:
10 - Srinivas Kandagatla <srinivas.kandagatla@li 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 11
12 description: 12 description:
13 Top Level Mode Multiplexer pin controller in 13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14 (LPASS) Low Power Island (LPI) of Qualcomm S 14 (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 const: qcom,sc8280xp-lpass-lpi-pinctrl 18 const: qcom,sc8280xp-lpass-lpi-pinctrl
19 19
20 reg: 20 reg:
21 items: 21 items:
22 - description: LPASS LPI TLMM Control an 22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers 23 - description: LPASS LPI MCC registers
24 24
25 clocks: 25 clocks:
26 items: 26 items:
27 - description: LPASS Core voting clock 27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock 28 - description: LPASS Audio voting clock
29 29
30 clock-names: 30 clock-names:
31 items: 31 items:
32 - const: core 32 - const: core
33 - const: audio 33 - const: audio
34 34
>> 35 gpio-controller: true
>> 36
>> 37 "#gpio-cells":
>> 38 description: Specifying the pin number and flags, as defined in
>> 39 include/dt-bindings/gpio/gpio.h
>> 40 const: 2
>> 41
>> 42 gpio-ranges:
>> 43 maxItems: 1
>> 44
35 patternProperties: 45 patternProperties:
36 "-state$": 46 "-state$":
37 oneOf: 47 oneOf:
38 - $ref: "#/$defs/qcom-sc8280xp-lpass-sta 48 - $ref: "#/$defs/qcom-sc8280xp-lpass-state"
39 - patternProperties: 49 - patternProperties:
40 "-pins$": 50 "-pins$":
41 $ref: "#/$defs/qcom-sc8280xp-lpass 51 $ref: "#/$defs/qcom-sc8280xp-lpass-state"
42 additionalProperties: false 52 additionalProperties: false
43 53
44 $defs: 54 $defs:
45 qcom-sc8280xp-lpass-state: 55 qcom-sc8280xp-lpass-state:
46 type: object 56 type: object
47 description: 57 description:
48 Pinctrl node's client devices use subnod 58 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standar 59 Client device subnodes use below standard properties.
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qc !! 60 $ref: /schemas/pinctrl/pincfg-node.yaml
51 unevaluatedProperties: false <<
52 61
53 properties: 62 properties:
54 pins: 63 pins:
55 description: 64 description:
56 List of gpio pins affected by the pr 65 List of gpio pins affected by the properties specified in this
57 subnode. 66 subnode.
58 items: 67 items:
59 pattern: "^gpio([0-9]|1[0-8])$" 68 pattern: "^gpio([0-9]|1[0-8])$"
60 69
61 function: 70 function:
62 enum: [ swr_tx_clk, swr_tx_data, swr_r 71 enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
63 dmic1_clk, dmic1_data, dmic2_c 72 dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
64 dmic4_data, i2s2_clk, i2s2_ws, 73 dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
65 qua_mi2s_sclk, qua_mi2s_ws, qu 74 qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
66 i2s1_data, wsa_swr_clk, wsa_sw 75 i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
67 wsa2_swr_data, i2s2_data, i2s3 76 wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
68 ext_mclk1_c, ext_mclk1_b, ext_ 77 ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
69 description: 78 description:
70 Specify the alternative function to 79 Specify the alternative function to be configured for the specified
71 pins. 80 pins.
72 81
>> 82 drive-strength:
>> 83 enum: [2, 4, 6, 8, 10, 12, 14, 16]
>> 84 default: 2
>> 85 description:
>> 86 Selects the drive strength for the specified pins, in mA.
>> 87
>> 88 slew-rate:
>> 89 enum: [0, 1, 2, 3]
>> 90 default: 0
>> 91 description: |
>> 92 0: No adjustments
>> 93 1: Higher Slew rate (faster edges)
>> 94 2: Lower Slew rate (slower edges)
>> 95 3: Reserved (No adjustments)
>> 96
>> 97 bias-bus-hold: true
>> 98 bias-pull-down: true
>> 99 bias-pull-up: true
>> 100 bias-disable: true
>> 101 input-enable: true
>> 102 output-high: true
>> 103 output-low: true
>> 104
>> 105 required:
>> 106 - pins
>> 107 - function
>> 108
>> 109 additionalProperties: false
>> 110
73 allOf: 111 allOf:
74 - $ref: qcom,lpass-lpi-common.yaml# !! 112 - $ref: pinctrl.yaml#
75 113
76 required: 114 required:
77 - compatible 115 - compatible
78 - reg 116 - reg
79 - clocks 117 - clocks
80 - clock-names 118 - clock-names
>> 119 - gpio-controller
>> 120 - "#gpio-cells"
>> 121 - gpio-ranges
81 122
82 unevaluatedProperties: false !! 123 additionalProperties: false
83 124
84 examples: 125 examples:
85 - | 126 - |
86 #include <dt-bindings/sound/qcom,q6afe.h> 127 #include <dt-bindings/sound/qcom,q6afe.h>
87 pinctrl@33c0000 { 128 pinctrl@33c0000 {
88 compatible = "qcom,sc8280xp-lpass-lpi- 129 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
89 reg = <0x33c0000 0x20000>, 130 reg = <0x33c0000 0x20000>,
90 <0x3550000 0x10000>; 131 <0x3550000 0x10000>;
91 clocks = <&q6afecc LPASS_HW_MACRO_VOTE 132 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
92 <&q6afecc LPASS_HW_DCODEC_VOT 133 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
93 clock-names = "core", "audio"; 134 clock-names = "core", "audio";
94 gpio-controller; 135 gpio-controller;
95 #gpio-cells = <2>; 136 #gpio-cells = <2>;
96 gpio-ranges = <&lpi_tlmm 0 0 19>; 137 gpio-ranges = <&lpi_tlmm 0 0 19>;
97 138
98 dmic01-state { 139 dmic01-state {
99 dmic01-clk-pins { 140 dmic01-clk-pins {
100 pins = "gpio16"; 141 pins = "gpio16";
101 function = "dmic1_clk"; 142 function = "dmic1_clk";
102 }; 143 };
103 144
104 dmic01-clk-sleep-pins { 145 dmic01-clk-sleep-pins {
105 pins = "gpio16"; 146 pins = "gpio16";
106 function = "dmic1_clk"; 147 function = "dmic1_clk";
107 }; 148 };
108 }; 149 };
109 150
110 tx-swr-data-sleep-state { 151 tx-swr-data-sleep-state {
111 pins = "gpio0", "gpio1"; 152 pins = "gpio0", "gpio1";
112 function = "swr_tx_data"; 153 function = "swr_tx_data";
113 }; 154 };
114 }; 155 };
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