1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SM4250 SoC LPASS LPI TLMM 7 title: Qualcomm SM4250 SoC LPASS LPI TLMM
8 8
9 maintainers: 9 maintainers:
10 - Srinivas Kandagatla <srinivas.kandagatla@li 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 11
12 description: 12 description:
13 Top Level Mode Multiplexer pin controller in 13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14 (LPASS) Low Power Island (LPI) of Qualcomm S 14 (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 const: qcom,sm4250-lpass-lpi-pinctrl 18 const: qcom,sm4250-lpass-lpi-pinctrl
19 19
20 reg: 20 reg:
21 items: 21 items:
22 - description: LPASS LPI TLMM Control an 22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers 23 - description: LPASS LPI MCC registers
24 24
25 clocks: 25 clocks:
26 items: 26 items:
27 - description: LPASS Audio voting clock 27 - description: LPASS Audio voting clock
28 28
29 clock-names: 29 clock-names:
30 items: 30 items:
31 - const: audio 31 - const: audio
32 32
33 patternProperties: 33 patternProperties:
34 "-state$": 34 "-state$":
35 oneOf: 35 oneOf:
36 - $ref: "#/$defs/qcom-sm4250-lpass-state 36 - $ref: "#/$defs/qcom-sm4250-lpass-state"
37 - patternProperties: 37 - patternProperties:
38 "-pins$": 38 "-pins$":
39 $ref: "#/$defs/qcom-sm4250-lpass-s 39 $ref: "#/$defs/qcom-sm4250-lpass-state"
40 additionalProperties: false 40 additionalProperties: false
41 41
42 $defs: 42 $defs:
43 qcom-sm4250-lpass-state: 43 qcom-sm4250-lpass-state:
44 type: object 44 type: object
45 description: 45 description:
46 Pinctrl node's client devices use subnod 46 Pinctrl node's client devices use subnodes for desired pin configuration.
47 Client device subnodes use below standar 47 Client device subnodes use below standard properties.
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qc 48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
49 unevaluatedProperties: false 49 unevaluatedProperties: false
50 50
51 properties: 51 properties:
52 pins: 52 pins:
53 description: 53 description:
54 List of gpio pins affected by the pr 54 List of gpio pins affected by the properties specified in this
55 subnode. 55 subnode.
56 items: 56 items:
57 pattern: "^gpio([0-9]|1[0-9]|2[0-6]) 57 pattern: "^gpio([0-9]|1[0-9]|2[0-6])$"
58 58
59 function: 59 function:
60 enum: [ gpio, dmic01_clk, dmic01_data, 60 enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data,
61 dmic4_clk, dmic4_data, ext_mcl 61 dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1_a,
62 ext_mclk1_b, ext_mclk1_c, i2s1 62 ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws,
63 i2s2_clk, i2s2_data, i2s2_ws, 63 i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws,
64 qua_mi2s_data, qua_mi2s_sclk, 64 qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_data,
65 swr_rx_clk, swr_rx_data, swr_t 65 swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_clk,
66 swr_wsa_data ] 66 swr_wsa_data ]
67 description: 67 description:
68 Specify the alternative function to 68 Specify the alternative function to be configured for the specified
69 pins. 69 pins.
70 70
71 allOf: 71 allOf:
72 - $ref: qcom,lpass-lpi-common.yaml# 72 - $ref: qcom,lpass-lpi-common.yaml#
73 73
74 required: 74 required:
75 - compatible 75 - compatible
76 - reg 76 - reg
77 - clocks 77 - clocks
78 - clock-names 78 - clock-names
79 79
80 unevaluatedProperties: false 80 unevaluatedProperties: false
81 81
82 examples: 82 examples:
83 - | 83 - |
84 #include <dt-bindings/sound/qcom,q6afe.h> 84 #include <dt-bindings/sound/qcom,q6afe.h>
85 lpi_tlmm: pinctrl@a7c0000 { 85 lpi_tlmm: pinctrl@a7c0000 {
86 compatible = "qcom,sm4250-lpass-lpi-pi 86 compatible = "qcom,sm4250-lpass-lpi-pinctrl";
87 reg = <0xa7c0000 0x20000>, 87 reg = <0xa7c0000 0x20000>,
88 <0xa950000 0x10000>; 88 <0xa950000 0x10000>;
89 clocks = <&q6afecc LPASS_HW_DCODEC_VOT 89 clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
90 clock-names = "audio"; 90 clock-names = "audio";
91 gpio-controller; 91 gpio-controller;
92 #gpio-cells = <2>; 92 #gpio-cells = <2>;
93 gpio-ranges = <&lpi_tlmm 0 0 19>; 93 gpio-ranges = <&lpi_tlmm 0 0 19>;
94 94
95 i2s2-active-state { 95 i2s2-active-state {
96 clk-pins { 96 clk-pins {
97 pins = "gpio10"; 97 pins = "gpio10";
98 function = "i2s2_clk"; 98 function = "i2s2_clk";
99 drive-strength = <2>; 99 drive-strength = <2>;
100 slew-rate = <1>; 100 slew-rate = <1>;
101 bias-disable; 101 bias-disable;
102 }; 102 };
103 103
104 data-pins { 104 data-pins {
105 pins = "gpio12"; 105 pins = "gpio12";
106 function = "i2s2_data"; 106 function = "i2s2_data";
107 drive-strength = <2>; 107 drive-strength = <2>;
108 slew-rate = <1>; 108 slew-rate = <1>;
109 }; 109 };
110 }; 110 };
111 111
112 i2s2-sleep-clk-state { 112 i2s2-sleep-clk-state {
113 pins = "gpio10"; 113 pins = "gpio10";
114 function = "i2s2_clk"; 114 function = "i2s2_clk";
115 drive-strength = <2>; 115 drive-strength = <2>;
116 bias-pull-down; 116 bias-pull-down;
117 }; 117 };
118 }; 118 };
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