1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SM7150 TLMM pin controller 7 title: Qualcomm SM7150 TLMM pin controller
8 8
9 maintainers: 9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org> 10 - Bjorn Andersson <andersson@kernel.org>
11 - Danila Tikhonov <danila@jiaxyga.com> 11 - Danila Tikhonov <danila@jiaxyga.com>
12 12
13 description: 13 description:
14 Top Level Mode Multiplexer pin controller in 14 Top Level Mode Multiplexer pin controller in Qualcomm SM7150 SoC.
15 15
16 allOf: 16 allOf:
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.ya 17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 const: qcom,sm7150-tlmm 21 const: qcom,sm7150-tlmm
22 22
23 reg: 23 reg:
24 maxItems: 3 24 maxItems: 3
25 25
26 reg-names: 26 reg-names:
27 items: 27 items:
28 - const: west 28 - const: west
29 - const: north 29 - const: north
30 - const: south 30 - const: south
31 31
32 interrupts: 32 interrupts:
33 maxItems: 1 33 maxItems: 1
34 34
>> 35 interrupt-controller: true
>> 36 "#interrupt-cells": true
>> 37 gpio-controller: true
>> 38 "#gpio-cells": true
>> 39 gpio-ranges: true
>> 40 wakeup-parent: true
>> 41
35 gpio-reserved-ranges: 42 gpio-reserved-ranges:
36 minItems: 1 43 minItems: 1
37 maxItems: 60 44 maxItems: 60
38 45
39 gpio-line-names: 46 gpio-line-names:
40 maxItems: 119 47 maxItems: 119
41 48
42 patternProperties: 49 patternProperties:
43 "-state$": 50 "-state$":
44 oneOf: 51 oneOf:
45 - $ref: "#/$defs/qcom-sm7150-tlmm-state" 52 - $ref: "#/$defs/qcom-sm7150-tlmm-state"
46 - patternProperties: 53 - patternProperties:
47 "-pins$": 54 "-pins$":
48 $ref: "#/$defs/qcom-sm7150-tlmm-st 55 $ref: "#/$defs/qcom-sm7150-tlmm-state"
49 additionalProperties: false 56 additionalProperties: false
50 57
51 $defs: 58 $defs:
52 qcom-sm7150-tlmm-state: 59 qcom-sm7150-tlmm-state:
53 type: object 60 type: object
54 description: 61 description:
55 Pinctrl node's client devices use subnod 62 Pinctrl node's client devices use subnodes for desired pin configuration.
56 Client device subnodes use below standar 63 Client device subnodes use below standard properties.
57 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tl 64 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58 unevaluatedProperties: false <<
59 65
60 properties: 66 properties:
61 pins: 67 pins:
62 description: 68 description:
63 List of gpio pins affected by the pr 69 List of gpio pins affected by the properties specified in this
64 subnode. 70 subnode.
65 items: 71 items:
66 oneOf: 72 oneOf:
67 - pattern: "^gpio([0-9]|[1-9][0-9] 73 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
68 - enum: [ sdc1_rclk, sdc1_clk, sdc 74 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
69 sdc2_cmd, sdc2_data, ufs 75 sdc2_cmd, sdc2_data, ufs_reset ]
70 minItems: 1 76 minItems: 1
71 maxItems: 36 77 maxItems: 36
72 78
73 function: 79 function:
74 description: 80 description:
75 Specify the alternative function to 81 Specify the alternative function to be configured for the specified
76 pins. 82 pins.
77 83
78 enum: [ gpio, adsp_ext, agera_pll, aos 84 enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
79 atest_tsens2, atest_usb1, ates 85 atest_tsens2, atest_usb1, atest_usb2, cam_mclk, cci_async,
80 cci_i2c, cci_timer0, cci_timer 86 cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
81 cci_timer4, dbg_out, ddr_bist, 87 cci_timer4, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2,
82 ddr_pxi3, edp_hot, edp_lcd, gc 88 ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0,
83 gp_pdm1, gp_pdm2, gps_tx, jitt 89 gp_pdm1, gp_pdm2, gps_tx, jitter_bist, ldo_en, ldo_update,
84 m_voc, mdp_vsync, mdp_vsync0, 90 m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
85 mdp_vsync3, mss_lte, nav_pps_i 91 mdp_vsync3, mss_lte, nav_pps_in, nav_pps_out, pa_indicator,
86 pci_e, phase_flag, pll_bist, p 92 pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s,
87 pri_mi2s_ws, prng_rosc, qdss, 93 pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
88 qlink_request, qua_mi2s, qup00 94 qlink_request, qua_mi2s, qup00, qup01, qup02, qup03, qup04,
89 qup10, qup11, qup12, qup13, qu 95 qup10, qup11, qup12, qup13, qup14, qup15, sd_write, sdc40,
90 sdc41, sdc42, sdc43, sdc4_clk, 96 sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, ter_mi2s,
91 tgu_ch0, tgu_ch1, tgu_ch2, tgu 97 tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsif1_clk, tsif1_data,
92 tsif1_en, tsif1_error, tsif1_s 98 tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, tsif2_data,
93 tsif2_en, tsif2_error, tsif2_s 99 tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data,
94 uim1_present, uim1_reset, uim2 100 uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
95 uim2_reset, uim_batt, usb_phy, 101 uim2_reset, uim_batt, usb_phy, vfr_1, vsense_trigger,
96 wlan1_adc0, wlan1_adc1, wlan2_ 102 wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk,
97 wsa_data ] 103 wsa_data ]
98 104
>> 105 bias-pull-down: true
>> 106 bias-pull-up: true
>> 107 bias-disable: true
>> 108 drive-strength: true
>> 109 input-enable: true
>> 110 output-high: true
>> 111 output-low: true
>> 112
99 required: 113 required:
100 - pins 114 - pins
101 115
>> 116 additionalProperties: false
>> 117
102 required: 118 required:
103 - compatible 119 - compatible
104 - reg 120 - reg
105 - reg-names 121 - reg-names
106 122
107 unevaluatedProperties: false !! 123 additionalProperties: false
108 124
109 examples: 125 examples:
110 - | 126 - |
111 #include <dt-bindings/interrupt-controller 127 #include <dt-bindings/interrupt-controller/arm-gic.h>
112 128
113 tlmm: pinctrl@3500000 { 129 tlmm: pinctrl@3500000 {
114 compatible = "qcom,sm7150-tlmm"; 130 compatible = "qcom,sm7150-tlmm";
115 reg = <0x03500000 0x300000>, 131 reg = <0x03500000 0x300000>,
116 <0x03900000 0x300000>, 132 <0x03900000 0x300000>,
117 <0x03d00000 0x300000>; 133 <0x03d00000 0x300000>;
118 reg-names = "west", "north", "south"; 134 reg-names = "west", "north", "south";
119 interrupts = <GIC_SPI 208 IRQ_TYPE_LEV 135 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
120 gpio-ranges = <&tlmm 0 0 120>; 136 gpio-ranges = <&tlmm 0 0 120>;
121 gpio-controller; 137 gpio-controller;
122 #gpio-cells = <2>; 138 #gpio-cells = <2>;
123 interrupt-controller; 139 interrupt-controller;
124 #interrupt-cells = <2>; 140 #interrupt-cells = <2>;
125 wakeup-parent = <&pdc>; 141 wakeup-parent = <&pdc>;
126 142
127 gpio-wo-state { 143 gpio-wo-state {
128 pins = "gpio1"; 144 pins = "gpio1";
129 function = "gpio"; 145 function = "gpio";
130 }; 146 };
131 147
132 uart-w-state { 148 uart-w-state {
133 rx-pins { 149 rx-pins {
134 pins = "gpio44"; 150 pins = "gpio44";
135 function = "qup12"; 151 function = "qup12";
136 bias-pull-up; 152 bias-pull-up;
137 }; 153 };
138 154
139 tx-pins { 155 tx-pins {
140 pins = "gpio45"; 156 pins = "gpio45";
141 function = "qup12"; 157 function = "qup12";
142 bias-disable; 158 bias-disable;
143 }; 159 };
144 }; 160 };
145 }; 161 };
146 ... 162 ...
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