1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SM8350 SoC LPASS LPI TLMM 7 title: Qualcomm SM8350 SoC LPASS LPI TLMM
8 8
9 maintainers: 9 maintainers:
10 - Krzysztof Kozlowski <krzysztof.kozlowski@li 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@li 11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12 12
13 description: 13 description:
14 Top Level Mode Multiplexer pin controller in 14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
15 (LPASS) Low Power Island (LPI) of Qualcomm S 15 (LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 const: qcom,sm8350-lpass-lpi-pinctrl 19 const: qcom,sm8350-lpass-lpi-pinctrl
20 20
21 reg: 21 reg:
22 items: 22 items:
23 - description: LPASS LPI TLMM Control an 23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers 24 - description: LPASS LPI MCC registers
25 25
26 clocks: 26 clocks:
27 items: 27 items:
28 - description: LPASS Core voting clock 28 - description: LPASS Core voting clock
29 - description: LPASS Audio voting clock 29 - description: LPASS Audio voting clock
30 30
31 clock-names: 31 clock-names:
32 items: 32 items:
33 - const: core 33 - const: core
34 - const: audio 34 - const: audio
35 35
>> 36 gpio-controller: true
>> 37
>> 38 "#gpio-cells":
>> 39 description: Specifying the pin number and flags, as defined in
>> 40 include/dt-bindings/gpio/gpio.h
>> 41 const: 2
>> 42
>> 43 gpio-ranges:
>> 44 maxItems: 1
>> 45
36 patternProperties: 46 patternProperties:
37 "-state$": 47 "-state$":
38 oneOf: 48 oneOf:
39 - $ref: "#/$defs/qcom-sm8350-lpass-state 49 - $ref: "#/$defs/qcom-sm8350-lpass-state"
40 - patternProperties: 50 - patternProperties:
41 "-pins$": 51 "-pins$":
42 $ref: "#/$defs/qcom-sm8350-lpass-s 52 $ref: "#/$defs/qcom-sm8350-lpass-state"
43 additionalProperties: false 53 additionalProperties: false
44 54
45 $defs: 55 $defs:
46 qcom-sm8350-lpass-state: 56 qcom-sm8350-lpass-state:
47 type: object 57 type: object
48 description: 58 description:
49 Pinctrl node's client devices use subnod 59 Pinctrl node's client devices use subnodes for desired pin configuration.
50 Client device subnodes use below standar 60 Client device subnodes use below standard properties.
51 $ref: qcom,lpass-lpi-common.yaml#/$defs/qc !! 61 $ref: /schemas/pinctrl/pincfg-node.yaml
52 unevaluatedProperties: false <<
53 62
54 properties: 63 properties:
55 pins: 64 pins:
56 description: 65 description:
57 List of gpio pins affected by the pr 66 List of gpio pins affected by the properties specified in this
58 subnode. 67 subnode.
59 items: 68 items:
60 pattern: "^gpio([0-9]|1[0-9]|2[0-2]) 69 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
61 70
62 function: 71 function:
63 enum: [ dmic1_clk, dmic1_data, dmic2_c 72 enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
64 dmic3_data, dmic4_clk, dmic4_d 73 dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
65 ext_mclk1_c, ext_mclk1_d, ext_ 74 ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
66 i2s0_data, i2s0_ws, i2s1_clk, 75 i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
67 i2s2_data, i2s2_ws, i2s3_clk, 76 i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
68 i2s4_data, i2s4_ws, slimbus_cl 77 i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk,
69 swr_rx_data, swr_tx_clk, swr_t 78 swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
70 wsa_swr_data, wsa2_swr_clk, ws 79 wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
71 description: 80 description:
72 Specify the alternative function to 81 Specify the alternative function to be configured for the specified
73 pins. 82 pins.
74 83
>> 84 drive-strength:
>> 85 enum: [2, 4, 6, 8, 10, 12, 14, 16]
>> 86 default: 2
>> 87 description:
>> 88 Selects the drive strength for the specified pins, in mA.
>> 89
>> 90 slew-rate:
>> 91 enum: [0, 1, 2, 3]
>> 92 default: 0
>> 93 description: |
>> 94 0: No adjustments
>> 95 1: Higher Slew rate (faster edges)
>> 96 2: Lower Slew rate (slower edges)
>> 97 3: Reserved (No adjustments)
>> 98
>> 99 bias-bus-hold: true
>> 100 bias-pull-down: true
>> 101 bias-pull-up: true
>> 102 bias-disable: true
>> 103 input-enable: true
>> 104 output-high: true
>> 105 output-low: true
>> 106
>> 107 required:
>> 108 - pins
>> 109 - function
>> 110
>> 111 additionalProperties: false
>> 112
75 allOf: 113 allOf:
76 - $ref: qcom,lpass-lpi-common.yaml# !! 114 - $ref: pinctrl.yaml#
77 115
78 required: 116 required:
79 - compatible 117 - compatible
80 - reg 118 - reg
81 - clocks 119 - clocks
82 - clock-names 120 - clock-names
>> 121 - gpio-controller
>> 122 - "#gpio-cells"
>> 123 - gpio-ranges
83 124
84 unevaluatedProperties: false !! 125 additionalProperties: false
85 126
86 examples: 127 examples:
87 - | 128 - |
88 #include <dt-bindings/sound/qcom,q6afe.h> 129 #include <dt-bindings/sound/qcom,q6afe.h>
89 130
90 lpass_tlmm: pinctrl@33c0000 { 131 lpass_tlmm: pinctrl@33c0000 {
91 compatible = "qcom,sm8350-lpass-lpi-pi 132 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
92 reg = <0x033c0000 0x20000>, 133 reg = <0x033c0000 0x20000>,
93 <0x03550000 0x10000>; 134 <0x03550000 0x10000>;
94 135
95 clocks = <&q6afecc LPASS_HW_MACRO_VOTE 136 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
96 <&q6afecc LPASS_HW_DCODEC_VOT 137 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
97 clock-names = "core", "audio"; 138 clock-names = "core", "audio";
98 139
99 gpio-controller; 140 gpio-controller;
100 #gpio-cells = <2>; 141 #gpio-cells = <2>;
101 gpio-ranges = <&lpass_tlmm 0 0 15>; 142 gpio-ranges = <&lpass_tlmm 0 0 15>;
102 }; 143 };
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