1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Technologies, Inc. SM8450 TLMM 7 title: Qualcomm Technologies, Inc. SM8450 TLMM block
8 8
9 maintainers: 9 maintainers:
10 - Vinod Koul <vkoul@kernel.org> 10 - Vinod Koul <vkoul@kernel.org>
11 11
12 description: 12 description:
13 Top Level Mode Multiplexer pin controller in 13 Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
14 14
15 allOf: 15 allOf:
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.ya 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 const: qcom,sm8450-tlmm 20 const: qcom,sm8450-tlmm
21 21
22 reg: 22 reg:
23 maxItems: 1 23 maxItems: 1
24 24
25 interrupts: 25 interrupts:
26 maxItems: 1 26 maxItems: 1
27 27
>> 28 interrupt-controller: true
>> 29 "#interrupt-cells": true
>> 30 gpio-controller: true
>> 31
28 gpio-reserved-ranges: 32 gpio-reserved-ranges:
29 minItems: 1 33 minItems: 1
30 maxItems: 105 34 maxItems: 105
31 35
32 gpio-line-names: 36 gpio-line-names:
33 maxItems: 210 37 maxItems: 210
34 38
>> 39 "#gpio-cells": true
>> 40 gpio-ranges: true
>> 41 wakeup-parent: true
>> 42
>> 43 required:
>> 44 - compatible
>> 45 - reg
>> 46
>> 47 additionalProperties: false
>> 48
35 patternProperties: 49 patternProperties:
36 "-state$": 50 "-state$":
37 oneOf: 51 oneOf:
38 - $ref: "#/$defs/qcom-sm8450-tlmm-state" 52 - $ref: "#/$defs/qcom-sm8450-tlmm-state"
39 - patternProperties: 53 - patternProperties:
40 "-pins$": 54 "-pins$":
41 $ref: "#/$defs/qcom-sm8450-tlmm-st 55 $ref: "#/$defs/qcom-sm8450-tlmm-state"
42 additionalProperties: false 56 additionalProperties: false
43 57
44 $defs: 58 $defs:
45 qcom-sm8450-tlmm-state: 59 qcom-sm8450-tlmm-state:
46 type: object 60 type: object
47 description: 61 description:
48 Pinctrl node's client devices use subnod 62 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standar 63 Client device subnodes use below standard properties.
50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tl 64 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false 65 unevaluatedProperties: false
52 66
53 properties: 67 properties:
54 pins: 68 pins:
55 description: 69 description:
56 List of gpio pins affected by the pr 70 List of gpio pins affected by the properties specified in this
57 subnode. 71 subnode.
58 items: 72 items:
59 oneOf: 73 oneOf:
60 - pattern: "^gpio([0-9]|[1-9][0-9] 74 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
61 - enum: [ ufs_reset, sdc2_clk, sdc 75 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62 minItems: 1 76 minItems: 1
63 maxItems: 36 77 maxItems: 36
64 78
65 function: 79 function:
66 description: 80 description:
67 Specify the alternative function to 81 Specify the alternative function to be configured for the specified
68 pins. 82 pins.
69 enum: [ aon_cam, atest_char, atest_usb 83 enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
70 cci_i2c, cci_timer, cmu_rng, c 84 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
71 cri_trng0, cri_trng1, dbg_out, 85 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
72 ddr_pxi2, ddr_pxi3, dp_hot, gc 86 ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
73 gpio, ibi_i3c, jitter_bist, md 87 gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
74 mdp_vsync2, mdp_vsync3, mi2s0_ 88 mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
75 mi2s0_ws, mi2s2_data0, mi2s2_d 89 mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
76 mss_grfc0, mss_grfc1, mss_grfc 90 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
77 mss_grfc2, mss_grfc3, mss_grfc 91 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
78 mss_grfc7, mss_grfc8, mss_grfc 92 mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
79 pcie1_clkreqn, phase_flag, pll 93 pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
80 prng_rosc, qdss_cti, qdss_gpio 94 prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
81 qlink0_wmss, qlink1_enable, ql 95 qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
82 qlink2_enable, qlink2_request, 96 qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
83 qspi2, qspi3, qspi_clk, qspi_c 97 qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
84 qup12, qup13, qup14, qup15, qu 98 qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
85 qup20, qup21, qup3, qup4, qup5 99 qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
86 qup_l5, qup_l6, sd_write, sdc4 100 qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
87 sdc4_cmd, sec_mi2s, tb_trig, t 101 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
88 tgu_ch3, tmess_prng0, tmess_pr 102 tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
89 tsense_pwm1, tsense_pwm2, uim0 103 tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
90 uim0_reset, uim1_clk, uim1_dat 104 uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
91 usb2phy_ac, usb_phy, vfr_0, vf 105 usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
92 106
93 required: 107 required:
94 - pins 108 - pins
95 <<
96 required: <<
97 - compatible <<
98 - reg <<
99 <<
100 unevaluatedProperties: false <<
101 109
102 examples: 110 examples:
103 - | 111 - |
104 #include <dt-bindings/interrupt-controller 112 #include <dt-bindings/interrupt-controller/arm-gic.h>
105 pinctrl@f100000 { 113 pinctrl@f100000 {
106 compatible = "qcom,sm8450-tlmm"; 114 compatible = "qcom,sm8450-tlmm";
107 reg = <0x0f100000 0x300000>; 115 reg = <0x0f100000 0x300000>;
108 gpio-controller; 116 gpio-controller;
109 #gpio-cells = <2>; 117 #gpio-cells = <2>;
110 gpio-ranges = <&tlmm 0 0 211>; 118 gpio-ranges = <&tlmm 0 0 211>;
111 interrupt-controller; 119 interrupt-controller;
112 #interrupt-cells = <2>; 120 #interrupt-cells = <2>;
113 interrupts = <GIC_SPI 208 IRQ_TYPE_LEV 121 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
114 122
115 gpio-wo-state { 123 gpio-wo-state {
116 pins = "gpio1"; 124 pins = "gpio1";
117 function = "gpio"; 125 function = "gpio";
118 }; 126 };
119 127
120 uart-w-state { 128 uart-w-state {
121 rx-pins { 129 rx-pins {
122 pins = "gpio26"; 130 pins = "gpio26";
123 function = "qup7"; 131 function = "qup7";
124 bias-pull-up; 132 bias-pull-up;
125 }; 133 };
126 134
127 tx-pins { 135 tx-pins {
128 pins = "gpio27"; 136 pins = "gpio27";
129 function = "qup7"; 137 function = "qup7";
130 bias-disable; 138 bias-disable;
131 }; 139 };
132 }; 140 };
133 }; 141 };
134 ... 142 ...
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