1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
8
9 maintainers:
10 - Krzysztof Kozlowski <krzysztof.kozlowski@li
11 - Srinivas Kandagatla <srinivas.kandagatla@li
12
13 description:
14 Top Level Mode Multiplexer pin controller in
15 (LPASS) Low Power Island (LPI) of Qualcomm S
16
17 properties:
18 compatible:
19 oneOf:
20 - const: qcom,sm8550-lpass-lpi-pinctrl
21 - items:
22 - const: qcom,x1e80100-lpass-lpi-pin
23 - const: qcom,sm8550-lpass-lpi-pinct
24
25 reg:
26 items:
27 - description: LPASS LPI TLMM Control an
28 - description: LPASS LPI MCC registers
29
30 clocks:
31 items:
32 - description: LPASS Core voting clock
33 - description: LPASS Audio voting clock
34
35 clock-names:
36 items:
37 - const: core
38 - const: audio
39
40 patternProperties:
41 "-state$":
42 oneOf:
43 - $ref: "#/$defs/qcom-sm8550-lpass-state
44 - patternProperties:
45 "-pins$":
46 $ref: "#/$defs/qcom-sm8550-lpass-s
47 additionalProperties: false
48
49 $defs:
50 qcom-sm8550-lpass-state:
51 type: object
52 description:
53 Pinctrl node's client devices use subnod
54 Client device subnodes use below standar
55 $ref: qcom,lpass-lpi-common.yaml#/$defs/qc
56 unevaluatedProperties: false
57
58 properties:
59 pins:
60 description:
61 List of gpio pins affected by the pr
62 subnode.
63 items:
64 pattern: "^gpio([0-9]|1[0-9]|2[0-2])
65
66 function:
67 enum: [ dmic1_clk, dmic1_data, dmic2_c
68 dmic3_data, dmic4_clk, dmic4_d
69 ext_mclk1_c, ext_mclk1_d, ext_
70 i2s0_data, i2s0_ws, i2s1_clk,
71 i2s2_data, i2s2_ws, i2s3_clk,
72 i2s4_data, i2s4_ws, slimbus_cl
73 swr_rx_data, swr_tx_clk, swr_t
74 wsa_swr_data, wsa2_swr_clk, ws
75 description:
76 Specify the alternative function to
77 pins.
78
79 allOf:
80 - $ref: qcom,lpass-lpi-common.yaml#
81
82 required:
83 - compatible
84 - reg
85 - clocks
86 - clock-names
87
88 unevaluatedProperties: false
89
90 examples:
91 - |
92 #include <dt-bindings/sound/qcom,q6dsp-lpa
93
94 lpass_tlmm: pinctrl@6e80000 {
95 compatible = "qcom,sm8550-lpass-lpi-pi
96 reg = <0x06e80000 0x20000>,
97 <0x0725a000 0x10000>;
98
99 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE
100 <&q6prmcc LPASS_HW_DCODEC_VOT
101 clock-names = "core", "audio";
102
103 gpio-controller;
104 #gpio-cells = <2>;
105 gpio-ranges = <&lpass_tlmm 0 0 23>;
106
107 tx-swr-sleep-clk-state {
108 pins = "gpio0";
109 function = "swr_tx_clk";
110 drive-strength = <2>;
111 bias-pull-down;
112 };
113 };
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