1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM 7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
8 8
9 maintainers: 9 maintainers:
10 - Krzysztof Kozlowski <krzysztof.kozlowski@li 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@li 11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12 12
13 description: 13 description:
14 Top Level Mode Multiplexer pin controller in 14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
15 (LPASS) Low Power Island (LPI) of Qualcomm S 15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 oneOf: !! 19 const: qcom,sm8550-lpass-lpi-pinctrl
20 - const: qcom,sm8550-lpass-lpi-pinctrl <<
21 - items: <<
22 - const: qcom,x1e80100-lpass-lpi-pin <<
23 - const: qcom,sm8550-lpass-lpi-pinct <<
24 20
25 reg: 21 reg:
26 items: 22 items:
27 - description: LPASS LPI TLMM Control an 23 - description: LPASS LPI TLMM Control and Status registers
28 - description: LPASS LPI MCC registers !! 24 - description: LPASS LPI pins SLEW registers
29 25
30 clocks: 26 clocks:
31 items: 27 items:
32 - description: LPASS Core voting clock 28 - description: LPASS Core voting clock
33 - description: LPASS Audio voting clock 29 - description: LPASS Audio voting clock
34 30
35 clock-names: 31 clock-names:
36 items: 32 items:
37 - const: core 33 - const: core
38 - const: audio 34 - const: audio
39 35
>> 36 gpio-controller: true
>> 37
>> 38 "#gpio-cells":
>> 39 description: Specifying the pin number and flags, as defined in
>> 40 include/dt-bindings/gpio/gpio.h
>> 41 const: 2
>> 42
>> 43 gpio-ranges:
>> 44 maxItems: 1
>> 45
40 patternProperties: 46 patternProperties:
41 "-state$": 47 "-state$":
42 oneOf: 48 oneOf:
43 - $ref: "#/$defs/qcom-sm8550-lpass-state 49 - $ref: "#/$defs/qcom-sm8550-lpass-state"
44 - patternProperties: 50 - patternProperties:
45 "-pins$": 51 "-pins$":
46 $ref: "#/$defs/qcom-sm8550-lpass-s 52 $ref: "#/$defs/qcom-sm8550-lpass-state"
47 additionalProperties: false 53 additionalProperties: false
48 54
49 $defs: 55 $defs:
50 qcom-sm8550-lpass-state: 56 qcom-sm8550-lpass-state:
51 type: object 57 type: object
52 description: 58 description:
53 Pinctrl node's client devices use subnod 59 Pinctrl node's client devices use subnodes for desired pin configuration.
54 Client device subnodes use below standar 60 Client device subnodes use below standard properties.
55 $ref: qcom,lpass-lpi-common.yaml#/$defs/qc !! 61 $ref: /schemas/pinctrl/pincfg-node.yaml
56 unevaluatedProperties: false <<
57 62
58 properties: 63 properties:
59 pins: 64 pins:
60 description: 65 description:
61 List of gpio pins affected by the pr 66 List of gpio pins affected by the properties specified in this
62 subnode. 67 subnode.
63 items: 68 items:
64 pattern: "^gpio([0-9]|1[0-9]|2[0-2]) 69 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
65 70
66 function: 71 function:
67 enum: [ dmic1_clk, dmic1_data, dmic2_c 72 enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
68 dmic3_data, dmic4_clk, dmic4_d 73 dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
69 ext_mclk1_c, ext_mclk1_d, ext_ 74 ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
70 i2s0_data, i2s0_ws, i2s1_clk, 75 i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
71 i2s2_data, i2s2_ws, i2s3_clk, 76 i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
72 i2s4_data, i2s4_ws, slimbus_cl 77 i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk,
73 swr_rx_data, swr_tx_clk, swr_t 78 swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
74 wsa_swr_data, wsa2_swr_clk, ws 79 wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
75 description: 80 description:
76 Specify the alternative function to 81 Specify the alternative function to be configured for the specified
77 pins. 82 pins.
78 83
>> 84 drive-strength:
>> 85 enum: [2, 4, 6, 8, 10, 12, 14, 16]
>> 86 default: 2
>> 87 description:
>> 88 Selects the drive strength for the specified pins, in mA.
>> 89
>> 90 slew-rate:
>> 91 enum: [0, 1, 2, 3]
>> 92 default: 0
>> 93 description: |
>> 94 0: No adjustments
>> 95 1: Higher Slew rate (faster edges)
>> 96 2: Lower Slew rate (slower edges)
>> 97 3: Reserved (No adjustments)
>> 98
>> 99 bias-bus-hold: true
>> 100 bias-pull-down: true
>> 101 bias-pull-up: true
>> 102 bias-disable: true
>> 103 input-enable: true
>> 104 output-high: true
>> 105 output-low: true
>> 106
>> 107 required:
>> 108 - pins
>> 109 - function
>> 110
>> 111 additionalProperties: false
>> 112
79 allOf: 113 allOf:
80 - $ref: qcom,lpass-lpi-common.yaml# !! 114 - $ref: pinctrl.yaml#
81 115
82 required: 116 required:
83 - compatible 117 - compatible
84 - reg 118 - reg
85 - clocks 119 - clocks
86 - clock-names 120 - clock-names
>> 121 - gpio-controller
>> 122 - "#gpio-cells"
>> 123 - gpio-ranges
87 124
88 unevaluatedProperties: false !! 125 additionalProperties: false
89 126
90 examples: 127 examples:
91 - | 128 - |
92 #include <dt-bindings/sound/qcom,q6dsp-lpa 129 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
93 130
94 lpass_tlmm: pinctrl@6e80000 { 131 lpass_tlmm: pinctrl@6e80000 {
95 compatible = "qcom,sm8550-lpass-lpi-pi 132 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
96 reg = <0x06e80000 0x20000>, 133 reg = <0x06e80000 0x20000>,
97 <0x0725a000 0x10000>; 134 <0x0725a000 0x10000>;
98 135
99 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE 136 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
100 <&q6prmcc LPASS_HW_DCODEC_VOT 137 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
101 clock-names = "core", "audio"; 138 clock-names = "core", "audio";
102 139
103 gpio-controller; 140 gpio-controller;
104 #gpio-cells = <2>; 141 #gpio-cells = <2>;
105 gpio-ranges = <&lpass_tlmm 0 0 23>; 142 gpio-ranges = <&lpass_tlmm 0 0 23>;
106 143
107 tx-swr-sleep-clk-state { 144 tx-swr-sleep-clk-state {
108 pins = "gpio0"; 145 pins = "gpio0";
109 function = "swr_tx_clk"; 146 function = "swr_tx_clk";
110 drive-strength = <2>; 147 drive-strength = <2>;
111 bias-pull-down; 148 bias-pull-down;
112 }; 149 };
113 }; 150 };
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