1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qco
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Qualcomm SM8650 SoC LPASS LPI TLMM
8
9 maintainers:
10 - Krzysztof Kozlowski <krzysztof.kozlowski@li
11 - Srinivas Kandagatla <srinivas.kandagatla@li
12
13 description:
14 Top Level Mode Multiplexer pin controller in
15 (LPASS) Low Power Island (LPI) of Qualcomm S
16
17 properties:
18 compatible:
19 const: qcom,sm8650-lpass-lpi-pinctrl
20
21 reg:
22 items:
23 - description: LPASS LPI TLMM Control an
24
25 clocks:
26 items:
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
29
30 clock-names:
31 items:
32 - const: core
33 - const: audio
34
35 patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-sm8650-lpass-state
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-sm8650-lpass-s
42 additionalProperties: false
43
44 $defs:
45 qcom-sm8650-lpass-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnod
49 Client device subnodes use below standar
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qc
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the pr
57 subnode.
58 items:
59 pattern: "^gpio([0-9]|1[0-9]|2[0-2])
60
61 function:
62 enum: [ dmic1_clk, dmic1_data, dmic2_c
63 dmic3_data, dmic4_clk, dmic4_d
64 ext_mclk1_c, ext_mclk1_d, ext_
65 i2s0_data, i2s0_ws, i2s1_clk,
66 i2s2_data, i2s2_ws, i2s3_clk,
67 i2s4_data, i2s4_ws, qca_swr_cl
68 slimbus_data, swr_rx_clk, swr_
69 wsa_swr_clk, wsa_swr_data, wsa
70 description:
71 Specify the alternative function to
72 pins.
73
74 allOf:
75 - $ref: qcom,lpass-lpi-common.yaml#
76
77 required:
78 - compatible
79 - reg
80 - clocks
81 - clock-names
82
83 unevaluatedProperties: false
84
85 examples:
86 - |
87 #include <dt-bindings/sound/qcom,q6dsp-lpa
88
89 lpass_tlmm: pinctrl@6e80000 {
90 compatible = "qcom,sm8650-lpass-lpi-pi
91 reg = <0x06e80000 0x20000>;
92
93 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE
94 <&q6prmcc LPASS_HW_DCODEC_VOT
95 clock-names = "core", "audio";
96
97 gpio-controller;
98 #gpio-cells = <2>;
99 gpio-ranges = <&lpass_tlmm 0 0 23>;
100
101 tx-swr-sleep-clk-state {
102 pins = "gpio0";
103 function = "swr_tx_clk";
104 drive-strength = <2>;
105 bias-pull-down;
106 };
107 };
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