1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ren 4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Renesas RZ/N1 Pin Controller 7 title: Renesas RZ/N1 Pin Controller
8 8
9 maintainers: 9 maintainers:
10 - Fabrizio Castro <fabrizio.castro.jz@renesas !! 10 - Gareth Williams <gareth.williams.jx@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be 11 - Geert Uytterhoeven <geert+renesas@glider.be>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 items: 15 items:
16 - enum: 16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D 17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S 18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generi 19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
20 20
21 reg: 21 reg:
22 items: 22 items:
23 - description: GPIO Multiplexing Level1 23 - description: GPIO Multiplexing Level1 Register Block
24 - description: GPIO Multiplexing Level2 24 - description: GPIO Multiplexing Level2 Register Block
25 25
26 clocks: 26 clocks:
27 maxItems: 1 27 maxItems: 1
28 28
29 clock-names: 29 clock-names:
30 const: bus 30 const: bus
31 description: 31 description:
32 The bus clock, sometimes described as pc 32 The bus clock, sometimes described as pclk, for register accesses.
33 33
34 allOf: <<
35 - $ref: pinctrl.yaml# <<
36 <<
37 required: 34 required:
38 - compatible 35 - compatible
39 - reg 36 - reg
40 - clocks 37 - clocks
41 - clock-names 38 - clock-names
42 39
43 additionalProperties: 40 additionalProperties:
44 anyOf: 41 anyOf:
45 - type: object 42 - type: object
46 allOf: 43 allOf:
47 - $ref: pincfg-node.yaml# 44 - $ref: pincfg-node.yaml#
48 - $ref: pinmux-node.yaml# 45 - $ref: pinmux-node.yaml#
49 46
50 description: 47 description:
51 A pin multiplexing sub-node describes 48 A pin multiplexing sub-node describes how to configure a set of (or a
52 single) pin in some desired alternate 49 single) pin in some desired alternate function mode.
53 A single sub-node may define several p 50 A single sub-node may define several pin configurations.
54 51
55 properties: 52 properties:
56 pinmux: 53 pinmux:
57 description: | 54 description: |
58 Integer array representing pin num 55 Integer array representing pin number and pin multiplexing
59 configuration. 56 configuration.
60 When a pin has to be configured in 57 When a pin has to be configured in alternate function mode, use
61 this property to identify the pin 58 this property to identify the pin by its global index, and provide
62 its alternate function configurati 59 its alternate function configuration number along with it.
63 When multiple pins are required to 60 When multiple pins are required to be configured as part of the
64 same alternate function they shall 61 same alternate function they shall be specified as members of the
65 same argument list of a single "pi 62 same argument list of a single "pinmux" property.
66 Integers values in the "pinmux" ar 63 Integers values in the "pinmux" argument list are assembled as:
67 (PIN | MUX_FUNC << 8) 64 (PIN | MUX_FUNC << 8)
68 where PIN directly corresponds to 65 where PIN directly corresponds to the pl_gpio pin number and
69 MUX_FUNC is one of the alternate f 66 MUX_FUNC is one of the alternate function identifiers defined in:
70 <include/dt-bindings/pinctrl/rzn1- 67 <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
71 These identifiers collapse the IO 68 These identifiers collapse the IO Multiplex Configuration Level 1
72 and Level 2 numbers that are detai 69 and Level 2 numbers that are detailed in the hardware reference
73 manual into a single number. The i 70 manual into a single number. The identifiers for Level 2 are simply
74 offset by 10. Additional identifi 71 offset by 10. Additional identifiers are provided to specify the
75 MDIO source peripheral. 72 MDIO source peripheral.
76 73
>> 74 phandle: true
77 bias-disable: true 75 bias-disable: true
78 bias-pull-up: 76 bias-pull-up:
79 description: Pull up the pin with 50 77 description: Pull up the pin with 50 kOhm
80 bias-pull-down: 78 bias-pull-down:
81 description: Pull down the pin with 79 description: Pull down the pin with 50 kOhm
82 bias-high-impedance: true 80 bias-high-impedance: true
83 drive-strength: 81 drive-strength:
84 enum: [ 4, 6, 8, 12 ] 82 enum: [ 4, 6, 8, 12 ]
85 83
86 required: 84 required:
87 - pinmux 85 - pinmux
88 86
89 additionalProperties: 87 additionalProperties:
90 $ref: "#/additionalProperties/anyOf/0" 88 $ref: "#/additionalProperties/anyOf/0"
91 89
92 - type: object 90 - type: object
>> 91 properties:
>> 92 phandle: true
>> 93
93 additionalProperties: 94 additionalProperties:
94 $ref: "#/additionalProperties/anyOf/0" 95 $ref: "#/additionalProperties/anyOf/0"
95 96
96 examples: 97 examples:
97 - | 98 - |
98 #include <dt-bindings/clock/r9a06g032-sysc 99 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
99 #include <dt-bindings/pinctrl/rzn1-pinctrl 100 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
100 pinctrl: pinctrl@40067000 { 101 pinctrl: pinctrl@40067000 {
101 compatible = "renesas,r9a06g032-pi 102 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
102 reg = <0x40067000 0x1000>, <0x5100 103 reg = <0x40067000 0x1000>, <0x51000000 0x480>;
103 clocks = <&sysctrl R9A06G032_HCLK_ 104 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
104 clock-names = "bus"; 105 clock-names = "bus";
105 106
106 /* 107 /*
107 * A serial communication interfac 108 * A serial communication interface with a TX output pin and an RX
108 * input pin. 109 * input pin.
109 */ 110 */
110 pins_uart0: pins_uart0 { 111 pins_uart0: pins_uart0 {
111 pinmux = < 112 pinmux = <
112 RZN1_PINMUX(103, R 113 RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
113 RZN1_PINMUX(104, R 114 RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
114 >; 115 >;
115 }; 116 };
116 117
117 /* 118 /*
118 * Set the pull-up on the RXD pin 119 * Set the pull-up on the RXD pin of the UART.
119 */ 120 */
120 pins_uart0_alt: pins_uart0_alt { 121 pins_uart0_alt: pins_uart0_alt {
121 pinmux = <RZN1_PINMUX(103, 122 pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
122 123
123 pins_uart6_rx { 124 pins_uart6_rx {
124 pinmux = <RZN1_PIN 125 pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
125 bias-pull-up; 126 bias-pull-up;
126 }; 127 };
127 }; 128 };
128 }; 129 };
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