1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sta 4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: StarFive JH7110 SYS Pin Controller 7 title: StarFive JH7110 SYS Pin Controller
8 8
9 description: | 9 description: |
10 Bindings for the JH7110 RISC-V SoC from Star 10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
11 11
12 Out of the SoC's many pins only the ones nam 12 Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63
13 can be multiplexed and have configurable bia 13 can be multiplexed and have configurable bias, drive strength,
14 schmitt trigger etc. 14 schmitt trigger etc.
15 Some peripherals have their I/O go through t 15 Some peripherals have their I/O go through the 64 "GPIOs". This also
16 includes a number of other UARTs, I2Cs, SPIs 16 includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
17 All these peripherals are connected to all 6 17 All these peripherals are connected to all 64 GPIOs such that
18 any GPIO can be set up to be controlled by a 18 any GPIO can be set up to be controlled by any of the peripherals.
19 19
20 maintainers: 20 maintainers:
21 - Jianlong Huang <jianlong.huang@starfivetech 21 - Jianlong Huang <jianlong.huang@starfivetech.com>
22 22
23 properties: 23 properties:
24 compatible: 24 compatible:
25 const: starfive,jh7110-sys-pinctrl 25 const: starfive,jh7110-sys-pinctrl
26 26
27 reg: 27 reg:
28 maxItems: 1 28 maxItems: 1
29 29
30 clocks: 30 clocks:
31 maxItems: 1 31 maxItems: 1
32 32
33 resets: 33 resets:
34 maxItems: 1 34 maxItems: 1
35 35
36 interrupts: 36 interrupts:
37 maxItems: 1 37 maxItems: 1
38 38
39 interrupt-controller: true 39 interrupt-controller: true
40 40
41 '#interrupt-cells': 41 '#interrupt-cells':
42 const: 2 42 const: 2
43 43
44 gpio-controller: true 44 gpio-controller: true
45 45
46 '#gpio-cells': 46 '#gpio-cells':
47 const: 2 47 const: 2
48 48
49 patternProperties: 49 patternProperties:
50 '-[0-9]+$': 50 '-[0-9]+$':
51 type: object 51 type: object
52 additionalProperties: false 52 additionalProperties: false
53 patternProperties: 53 patternProperties:
54 '-pins$': 54 '-pins$':
55 type: object 55 type: object
56 description: | 56 description: |
57 A pinctrl node should contain at lea 57 A pinctrl node should contain at least one subnode representing the
58 pinctrl groups available on the mach 58 pinctrl groups available on the machine. Each subnode will list the
59 pins it needs, and how they should b 59 pins it needs, and how they should be configured, with regard to
60 muxer configuration, bias, input ena 60 muxer configuration, bias, input enable/disable, input schmitt
61 trigger enable/disable, slew-rate an 61 trigger enable/disable, slew-rate and drive strength.
62 allOf: 62 allOf:
63 - $ref: /schemas/pinctrl/pincfg-node 63 - $ref: /schemas/pinctrl/pincfg-node.yaml
64 - $ref: /schemas/pinctrl/pinmux-node 64 - $ref: /schemas/pinctrl/pinmux-node.yaml
65 additionalProperties: false 65 additionalProperties: false
66 66
67 properties: 67 properties:
68 pinmux: 68 pinmux:
69 description: | 69 description: |
70 The list of GPIOs and their mux 70 The list of GPIOs and their mux settings that properties in the
71 node apply to. This should be se 71 node apply to. This should be set using the GPIOMUX or PINMUX
72 macros. 72 macros.
73 73
74 bias-disable: true 74 bias-disable: true
75 75
76 bias-pull-up: 76 bias-pull-up:
77 type: boolean 77 type: boolean
78 78
79 bias-pull-down: 79 bias-pull-down:
80 type: boolean 80 type: boolean
81 81
82 drive-strength: 82 drive-strength:
83 enum: [ 2, 4, 8, 12 ] 83 enum: [ 2, 4, 8, 12 ]
84 84
85 input-enable: true 85 input-enable: true
86 86
87 input-disable: true 87 input-disable: true
88 88
89 input-schmitt-enable: true 89 input-schmitt-enable: true
90 90
91 input-schmitt-disable: true 91 input-schmitt-disable: true
92 92
93 slew-rate: 93 slew-rate:
94 maximum: 1 94 maximum: 1
95 95
96 required: 96 required:
97 - compatible 97 - compatible
98 - reg 98 - reg
99 - clocks 99 - clocks
100 - interrupts 100 - interrupts
101 - interrupt-controller 101 - interrupt-controller
102 - '#interrupt-cells' 102 - '#interrupt-cells'
103 - gpio-controller 103 - gpio-controller
104 - '#gpio-cells' 104 - '#gpio-cells'
105 105
106 additionalProperties: false 106 additionalProperties: false
107 107
108 examples: 108 examples:
109 - | 109 - |
110 pinctrl@13040000 { 110 pinctrl@13040000 {
111 compatible = "starfive,jh7110-sys-pinc 111 compatible = "starfive,jh7110-sys-pinctrl";
112 reg = <0x13040000 0x10000>; 112 reg = <0x13040000 0x10000>;
113 clocks = <&syscrg 112>; 113 clocks = <&syscrg 112>;
114 resets = <&syscrg 2>; 114 resets = <&syscrg 2>;
115 interrupts = <86>; 115 interrupts = <86>;
116 interrupt-controller; 116 interrupt-controller;
117 #interrupt-cells = <2>; 117 #interrupt-cells = <2>;
118 gpio-controller; 118 gpio-controller;
119 #gpio-cells = <2>; 119 #gpio-cells = <2>;
120 120
121 uart0-0 { 121 uart0-0 {
122 tx-pins { 122 tx-pins {
123 pinmux = <0xff140005>; 123 pinmux = <0xff140005>;
124 bias-disable; 124 bias-disable;
125 drive-strength = <12>; 125 drive-strength = <12>;
126 input-disable; 126 input-disable;
127 input-schmitt-disable; 127 input-schmitt-disable;
128 slew-rate = <0>; 128 slew-rate = <0>;
129 }; 129 };
130 130
131 rx-pins { 131 rx-pins {
132 pinmux = <0x0E000406>; 132 pinmux = <0x0E000406>;
133 bias-pull-up; 133 bias-pull-up;
134 drive-strength = <2>; 134 drive-strength = <2>;
135 input-enable; 135 input-enable;
136 input-schmitt-enable; 136 input-schmitt-enable;
137 slew-rate = <0>; 137 slew-rate = <0>;
138 }; 138 };
139 }; 139 };
140 }; 140 };
141 141
142 ... 142 ...
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