1 Device-tree bindings for persistent memory reg 1 Device-tree bindings for persistent memory regions
2 ---------------------------------------------- 2 -----------------------------------------------------
3 3
4 Persistent memory refers to a class of memory 4 Persistent memory refers to a class of memory devices that are:
5 5
6 a) Usable as main system memory (i.e. 6 a) Usable as main system memory (i.e. cacheable), and
7 b) Retain their contents across power 7 b) Retain their contents across power failure.
8 8
9 Given b) it is best to think of persistent mem 9 Given b) it is best to think of persistent memory as a kind of memory mapped
10 storage device. To ensure data integrity the o 10 storage device. To ensure data integrity the operating system needs to manage
11 persistent regions separately to the normal me 11 persistent regions separately to the normal memory pool. To aid with that this
12 binding provides a standardised interface for 12 binding provides a standardised interface for discovering where persistent
13 memory regions exist inside the physical addre 13 memory regions exist inside the physical address space.
14 14
15 Bindings for the region nodes: 15 Bindings for the region nodes:
16 ----------------------------- 16 -----------------------------
17 17
18 Required properties: 18 Required properties:
19 - compatible = "pmem-region" 19 - compatible = "pmem-region"
20 20
21 - reg = <base, size>; 21 - reg = <base, size>;
22 The reg property should specif !! 22 The reg property should specificy an address range that is
23 translatable to a system physi 23 translatable to a system physical address range. This address
24 range should be mappable as no 24 range should be mappable as normal system memory would be
25 (i.e cacheable). 25 (i.e cacheable).
26 26
27 If the reg property contains m 27 If the reg property contains multiple address ranges
28 each address range will be tre 28 each address range will be treated as though it was specified
29 in a separate device node. Hav 29 in a separate device node. Having multiple address ranges in a
30 node implies no special relati 30 node implies no special relationship between the two ranges.
31 31
32 Optional properties: 32 Optional properties:
33 - Any relevant NUMA associativity prop !! 33 - Any relevant NUMA assocativity properties for the target platform.
34 34
35 - volatile; This property indicates th 35 - volatile; This property indicates that this region is actually
36 backed by non-persistent memory. Thi 36 backed by non-persistent memory. This lets the OS know that it
37 may skip the cache flushes required 37 may skip the cache flushes required to ensure data is made
38 persistent after a write. 38 persistent after a write.
39 39
40 If this property is absent then the 40 If this property is absent then the OS must assume that the region
41 is backed by non-volatile memory. 41 is backed by non-volatile memory.
42 42
43 Examples: 43 Examples:
44 -------------------- 44 --------------------
45 45
46 /* 46 /*
47 * This node specifies one 4KB region 47 * This node specifies one 4KB region spanning from
48 * 0x5000 to 0x5fff that is backed by 48 * 0x5000 to 0x5fff that is backed by non-volatile memory.
49 */ 49 */
50 pmem@5000 { 50 pmem@5000 {
51 compatible = "pmem-region"; 51 compatible = "pmem-region";
52 reg = <0x00005000 0x00001000>; 52 reg = <0x00005000 0x00001000>;
53 }; 53 };
54 54
55 /* 55 /*
56 * This node specifies two 4KB regions 56 * This node specifies two 4KB regions that are backed by
57 * volatile (normal) memory. 57 * volatile (normal) memory.
58 */ 58 */
59 pmem@6000 { 59 pmem@6000 {
60 compatible = "pmem-region"; 60 compatible = "pmem-region";
61 reg = < 0x00006000 0x00001000 61 reg = < 0x00006000 0x00001000
62 0x00008000 0x00001000 62 0x00008000 0x00001000 >;
63 volatile; 63 volatile;
64 }; 64 };
65 65
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