1 ==============================================
2 Power Architecture CPU Binding
3 Copyright 2013 Freescale Semiconductor Inc.
4
5 Power Architecture CPUs in Freescale SOCs are
6 per the definition in the Devicetree Specifica
7
8 In addition to the Devicetree Specification de
9 defined below may be present on CPU nodes.
10
11 PROPERTIES
12
13 - fsl,eref-*
14 Usage: optional
15 Value type: <empty>
16 Definition: The EREF (EREF: A Programm
17 Freescale Power Architecture) defines
18 Power CPUs. The EREF defines some arc
19 by the Power ISA. For these EREF-spec
20 a property named fsl,eref-[CAT], where
21 name with all uppercase letters conver
22 the category is supported by the imple
23
24 - fsl,portid-mapping
25 Usage: optional
26 Value type: <u32>
27 Definition: The Coherency Subdomain ID
28 Snoop ID Port Mapping registers, which
29 Coherency fabric (CCF), provide a Core
30 ID/CoreNet Snoop ID to cpu mapping fun
31 these registers should be set if the c
32 snooped. This property defines a bitm
33 that should be set if this cpu should
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