1 ============================================== 1 ===================================================================
2 Power Architecture CPU Binding 2 Power Architecture CPU Binding
3 Copyright 2013 Freescale Semiconductor Inc. 3 Copyright 2013 Freescale Semiconductor Inc.
4 4
5 Power Architecture CPUs in Freescale SOCs are 5 Power Architecture CPUs in Freescale SOCs are represented in device trees as
6 per the definition in the Devicetree Specifica !! 6 per the definition in ePAPR.
7 7
8 In addition to the Devicetree Specification de !! 8 In addition to the ePAPR definitions, the properties defined below may be
9 defined below may be present on CPU nodes. !! 9 present on CPU nodes.
10 10
11 PROPERTIES 11 PROPERTIES
12 12
13 - fsl,eref-* 13 - fsl,eref-*
14 Usage: optional 14 Usage: optional
15 Value type: <empty> 15 Value type: <empty>
16 Definition: The EREF (EREF: A Programm 16 Definition: The EREF (EREF: A Programmer.s Reference Manual for
17 Freescale Power Architecture) defines 17 Freescale Power Architecture) defines the architecture for Freescale
18 Power CPUs. The EREF defines some arc 18 Power CPUs. The EREF defines some architecture categories not defined
19 by the Power ISA. For these EREF-spec 19 by the Power ISA. For these EREF-specific categories, the existence of
20 a property named fsl,eref-[CAT], where 20 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
21 name with all uppercase letters conver 21 name with all uppercase letters converted to lowercase, indicates that
22 the category is supported by the imple 22 the category is supported by the implementation.
23 <<
24 - fsl,portid-mapping <<
25 Usage: optional <<
26 Value type: <u32> <<
27 Definition: The Coherency Subdomain ID <<
28 Snoop ID Port Mapping registers, which <<
29 Coherency fabric (CCF), provide a Core <<
30 ID/CoreNet Snoop ID to cpu mapping fun <<
31 these registers should be set if the c <<
32 snooped. This property defines a bitm <<
33 that should be set if this cpu should <<
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