1 MPC5200 Device Tree Bindings
2 ----------------------------
3
4 (c) 2006-2009 Secret Lab Technologies Ltd
5 Grant Likely <grant.likely@secretlab.ca>
6
7 Naming conventions
8 ------------------
9 For mpc5200 on-chip devices, the format for ea
10 <chip>-<device>[-<mode>]. The OS should be ab
11 to the device based solely on the compatible v
12 match on the compatible list; the 'most compat
13 selected.
14
15 The split between the MPC5200 and the MPC5200B
16 conundrum. How should the compatible property
17 maximum compatibility information; but still a
18 chip? For the MPC5200; the answer is easy. M
19 originally appeared on the MPC5200. Since the
20 else; the 5200 compatible properties will cont
21 "fsl,mpc5200-<device>".
22
23 The 5200B is almost the same as the 5200, but
24 silicon bugs and it adds a small number of enh
25 devices either provide exactly the same interf
26 devices have extra functions but still have a
27 To express this information as completely as p
28 should have two items in the compatible list:
29 compatible = "fsl,mpc5200b-<device>","
30
31 It is *strongly* recommended that 5200B device
32 (instead of only listing the base mpc5200 item
33
34 ie. ethernet on mpc5200: compatible = "fsl,mpc
35 ethernet on mpc5200b: compatible = "fsl,mp
36
37 Modal devices, like PSCs, also append the conf
38 end of the compatible field. ie. A PSC in i2s
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s".
40 avoid naming conflicts with non-psc devices pr
41 function. For example, "fsl,mpc5200-spi" and
42 the mpc5200 simple spi device and a PSC spi mo
43
44 At the time of writing, exact chip may be eith
45 'fsl,mpc5200b'.
46
47 The soc node
48 ------------
49 This node describes the on chip SOC peripheral
50 board will have this node, and as such there i
51 convention for SOC devices.
52
53 Required properties:
54 name description
55 ---- -----------
56 ranges Memory range of the in
57 Should be <0 [baseaddr
58 reg Should be <[baseaddr]
59 compatible mpc5200: "fsl,mpc5200-
60 mpc5200b: "fsl,mpc5200
61 system-frequency 'fsystem' frequency in
62 clocks are derived fro
63 bus-frequency IPB bus frequency in H
64 used by most of the so
65
66 soc child nodes
67 ---------------
68 Any on chip SOC devices available to Linux mus
69
70 Note: The tables below show the value for the
71 tree should use the "fsl,mpc5200b-<device>","f
72
73 Required soc5200 child nodes:
74 name compatible
75 ---- ----------
76 cdm@<addr> fsl,mpc5200-cd
77 interrupt-controller@<addr> fsl,mpc5200-pi
78
79 bestcomm@<addr> fsl,mpc5200-be
80
81 Recommended soc5200 child nodes; populate as n
82 name compatible Descri
83 ---- ---------- ------
84 timer@<addr> fsl,mpc5200-gpt Gener
85 gpio@<addr> fsl,mpc5200-gpio MPC52
86 gpio@<addr> fsl,mpc5200-gpio-wkup MPC52
87 rtc@<addr> fsl,mpc5200-rtc Real
88 mscan@<addr> fsl,mpc5200-mscan CAN b
89 pci@<addr> fsl,mpc5200-pci PCI b
90 serial@<addr> fsl,mpc5200-psc-uart PSC i
91 i2s@<addr> fsl,mpc5200-psc-i2s PSC i
92 ac97@<addr> fsl,mpc5200-psc-ac97 PSC i
93 spi@<addr> fsl,mpc5200-psc-spi PSC i
94 irda@<addr> fsl,mpc5200-psc-irda PSC i
95 spi@<addr> fsl,mpc5200-spi MPC52
96 ethernet@<addr> fsl,mpc5200-fec MPC52
97 ata@<addr> fsl,mpc5200-ata IDE A
98 i2c@<addr> fsl,mpc5200-i2c I2C c
99 usb@<addr> fsl,mpc5200-ohci,ohci-be USB c
100 xlb@<addr> fsl,mpc5200-xlb XLB a
101
102 fsl,mpc5200-gpt nodes
103 ---------------------
104 On the mpc5200 and 5200b, GPT0 has a watchdog
105 design supports the internal wdt, then the dev
106 include the empty property 'fsl,has-wdt'. Not
107 the watchdog. The timer will function as a GP
108 it will function as watchdog if the watchdog d
109 mode has priority over the gpt mode, i.e. if t
110 gpt api call to this timer will fail with -EBU
111
112 If you add the property
113 fsl,wdt-on-boot = <n>;
114 GPT0 will be marked as in-use watchdog, i.e. b
115 If n>0, the watchdog is started with a timeout
116 configuration of the watchdog is not touched.
117 - just mark GPT0 as watchdog, blocking gpt acc
118 - do not touch a configuration assigned by the
119 the boot process itself.
120
121 The watchdog will respect the CONFIG_WATCHDOG_
122
123 An mpc5200-gpt can be used as a single line GP
124 add the following properties to the gpt node:
125 gpio-controller;
126 #gpio-cells = <2>;
127 When referencing the GPIO line from another no
128 be zero and the second cell represents the gpi
129 gpio device tree binding.
130
131 An mpc5200-gpt can be used as a single line ed
132 controller. To do so, add the following prope
133 interrupt-controller;
134 #interrupt-cells = <1>;
135 When referencing the IRQ line from another nod
136 sense mode; 1 for edge rising, 2 for edge fall
137
138 fsl,mpc5200-psc nodes
139 ---------------------
140 The PSCs should include a cell-index which is
141 hardware. cell-index is used to determine whi
142 use when setting up PSC clocking. cell-index
143 PSC1 has 'cell-index = <0>'
144 PSC4 has 'cell-index = <3>'
145
146 PSC in i2s mode: The mpc5200 and mpc5200b PSC
147 i2s mode. An 'mpc5200b-psc-i2s' node cannot i
148 compatible field.
149
150
151 fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nod
152 ----------------------------------------------
153 Each GPIO controller node should have the empt
154 #gpio-cells set to 2. First cell is the GPIO n
155 according to the bit numbers in the GPIO contr
156 is for flags which is currently unused.
157
158 fsl,mpc5200-fec nodes
159 ---------------------
160 The FEC node can specify one of the following
161 the MII link:
162 - fsl,7-wire-mode - An empty property that spe
163 mode instead of MII
164 - current-speed - Specifies that the MII sho
165 speed. This property shou
166 first cell specifies the s
167 should be '0' for half dup
168 - phy-handle - Contains a phandle to an E
169
170 Interrupt controller (fsl,mpc5200-pic) node
171 -------------------------------------------
172 The mpc5200 pic binding splits hardware IRQ nu
173 split reflects the layout of the PIC hardware
174 interrupts into one of three groups; CRIT, MAI
175 Bestcomm dma engine has its own set of interru
176 cascaded off of peripheral interrupt 0, which
177 fourth group, SDMA.
178
179 The interrupts property for device nodes using
180 of three cells; <L1 L2 level>
181
182 L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
183 L2 := interrupt number; directly mapped fr
184 "ICTL PerStat, MainStat, CritStat En
185 level := [LEVEL_HIGH=0, EDGE_RISING=1, EDG
186
187 For external IRQs, use the following interrupt
188 specify external interrupts is a frequently as
189 External interrupts:
190 external irq0: interrupts = <0 0 n>;
191 external irq1: interrupts = <1 1 n>;
192 external irq2: interrupts = <1 2 n>;
193 external irq3: interrupts = <1 3 n>;
194 'n' is sense (0: level high, 1: edge rising, 2
195
196 fsl,mpc5200-mscan nodes
197 -----------------------
198 See file Documentation/devicetree/bindings/pow
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