1 ==============================================
2 Freescale MPIC Interrupt Controller Node
3 Copyright (C) 2010,2011 Freescale Semiconducto
4 ==============================================
5
6 The Freescale MPIC interrupt controller is fou
7 and QorIQ processors and is compatible with th
8 notable difference from Open PIC binding is th
9 additional cells in the interrupt specifier de
10 information.
11
12 PROPERTIES
13
14 - compatible
15 Usage: required
16 Value type: <string>
17 Definition: Shall include "fsl,mpic". F
18 controllers compatible with this bin
19 Revision Registers BRR1 and BRR2 at
20 0x10 in the MPIC.
21
22 - reg
23 Usage: required
24 Value type: <prop-encoded-array>
25 Definition: A standard property. Specif
26 offset and length of the device's re
27 CCSR address space.
28
29 - interrupt-controller
30 Usage: required
31 Value type: <empty>
32 Definition: Specifies that this node is
33 controller
34
35 - #interrupt-cells
36 Usage: required
37 Value type: <u32>
38 Definition: Shall be 2 or 4. A value of
39 specifiers do not contain the interr
40 information cells.
41
42 - #address-cells
43 Usage: required
44 Value type: <u32>
45 Definition: Shall be 0.
46
47 - pic-no-reset
48 Usage: optional
49 Value type: <empty>
50 Definition: The presence of this propert
51 MPIC must not be reset by the client
52 the boot program has initialized all
53 configuration registers to a sane st
54 directed at other cores. This ensur
55 program will not receive interrupts
56 to the client. The presence of this
57 that any initialization related to i
58 be limited to sources explicitly ref
59
60 - big-endian
61 Usage: optional
62 Value type: <empty>
63 If present the MPIC will be assumed
64 device-trees omit this property on M
65 in fact big-endian, so certain board
66
67 - single-cpu-affinity
68 Usage: optional
69 Value type: <empty>
70 If present the MPIC will be assumed
71 non-IPI interrupts to a single CPU a
72
73 - last-interrupt-source
74 Usage: optional
75 Value type: <u32>
76 Some MPICs do not correctly report t
77 in the global feature registers. If
78 override the value read from MPIC_GR
79
80 INTERRUPT SPECIFIER DEFINITION
81
82 Interrupt specifiers consists of 4 cells enc
83 follows:
84
85 <1st-cell> interrupt-number
86
87 Identifies the interrupt sourc
88 depends on the type of interru
89
90 Note: If the interrupt-type ce
91 (i.e. #interrupt-cells = 2), t
92 should be interpreted the same
93 interrupt-type 0-- i.e. an ext
94 normal SoC device interrupt.
95
96 <2nd-cell> level-sense information, encod
97 0 = low-to-high edge trigg
98 1 = active low level-sensi
99 2 = active high level-sens
100 3 = high-to-low edge trigg
101
102 <3rd-cell> interrupt-type
103
104 The following types are suppor
105
106 0 = external or normal SoC d
107
108 The interrupt-number cel
109 the SoC device interrupt
110 type-specific cell is un
111 interrupt-number is deri
112 MPIC a block of register
113 the "Interrupt Source Co
114 Each source has 32-bytes
115 (vector/priority and des
116 region. So interrupt 0
117 interrupt 1 is at offset
118
119 1 = error interrupt
120
121 The interrupt-number cel
122 the SoC device interrupt
123 the error interrupt. Th
124 cell identifies the spec
125 interrupt number.
126
127 2 = MPIC inter-processor int
128
129 The interrupt-number cel
130 the MPIC IPI number. Th
131 cell is undefined.
132
133 3 = MPIC timer interrupt
134
135 The interrupt-number cel
136 the MPIC timer number.
137 cell is undefined.
138
139 <4th-cell> type-specific information
140
141 The type-specific cell is enco
142
143 - For interrupt-type 1 (error
144 the type-specific cell cont
145 bit number of the error int
146 Error Interrupt Summary Reg
147
148 EXAMPLE 1
149 /*
150 * mpic interrupt controller with 4 ce
151 */
152 mpic: pic@40000 {
153 compatible = "fsl,mpic";
154 interrupt-controller;
155 #interrupt-cells = <4>;
156 #address-cells = <0>;
157 reg = <0x40000 0x40000>;
158 };
159
160 EXAMPLE 2
161 /*
162 * The MPC8544 I2C controller node has
163 * interrupt number of 27. As per the
164 * this corresponds to interrupt sourc
165 * registers at 0x5_0560.
166 *
167 * The interrupt source configuration
168 * at 0x5_0000.
169 *
170 * To compute the interrupt specifier
171 *
172 * 0x560 >> 5 = 43
173 *
174 * The interrupt source configuration
175 * at 0x5_0000, and so the i2c vector/
176 * are at 0x5_0560.
177 */
178 i2c@3000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 cell-index = <0>;
182 compatible = "fsl-i2c";
183 reg = <0x3000 0x100>;
184 interrupts = <43 2>;
185 interrupt-parent = <&mpic>;
186 dfsrr;
187 };
188
189
190 EXAMPLE 3
191 /*
192 * Definition of a node defining the
193 * MPIC IPI interrupts. Note the int
194 * type of 2.
195 */
196 ipi@410a0 {
197 compatible = "fsl,mpic-ipi";
198 reg = <0x40040 0x10>;
199 interrupts = <0 0 2 0
200 1 0 2 0
201 2 0 2 0
202 3 0 2 0>;
203 };
204
205 EXAMPLE 4
206 /*
207 * Definition of a node defining the
208 * global timers. Note the interrupt
209 * type of 3.
210 */
211 timer0: timer@41100 {
212 compatible = "fsl,mpic-global-
213 reg = <0x41100 0x100 0x41300 4
214 interrupts = <0 0 3 0
215 1 0 3 0
216 2 0 3 0
217 3 0 3 0>;
218 };
219
220 EXAMPLE 5
221 /*
222 * Definition of an error interrupt (i
223 * SoC interrupt number is 16 and the
224 * interrupt bit in the error interrup
225 * is 23.
226 */
227 memory-controller@8000 {
228 compatible = "fsl,p4080-memory
229 reg = <0x8000 0x1000>;
230 interrupts = <16 2 1 23>;
231 };
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