1 * Freescale MSI interrupt controller
2
3 Required properties:
4 - compatible : compatible list, may contain on
5 The first is "fsl,CHIP-msi", where CHIP is t
6 etc.) and the second is "fsl,mpic-msi" or "f
7 "fsl,mpic-msi-v4.3" depending on the parent
8 version is 4.3, the number of MSI registers
9 provided to access these 16 registers, and c
10 should be used. The first entry is optional;
11 required.
12
13 - reg : It may contain one or two regions. The
14 the address and the length of the shared mes
15 The second region should contain the address
16 register for platforms that have such an ali
17 region must be added because different MSI g
18
19 - interrupts : each one of the interrupts here
20 and routed to the host interrupt controller.
21 be set as edge sensitive. If msi-available-
22 the interrupts that correspond to available
23
24 Optional properties:
25 - msi-available-ranges: use <start count> styl
26 msi interrupt can be used in the 256 msi int
27 optional, without this, all the MSI interrup
28 Each available range must begin and end on a
29 no splitting an individual MSI register or t
30 MPIC v4.3 does not support this property bec
31 individual register are not continuous when
32
33 - msi-address-64: 64-bit PCI address of the MS
34 is used for MSI messaging. The address of M
35 the MSI message address.
36
37 This property may be used in virtualized env
38 has created an alternate mapping for the MSI
39 explanation.
40
41
42 Example:
43 msi@41600 {
44 compatible = "fsl,mpc8610-msi"
45 reg = <0x41600 0x80>;
46 msi-available-ranges = <0 0x10
47 interrupts = <
48 0xe0 0
49 0xe1 0
50 0xe2 0
51 0xe3 0
52 0xe4 0
53 0xe5 0
54 0xe6 0
55 0xe7 0>;
56 interrupt-parent = <&mpic>;
57 };
58
59 msi@41600 {
60 compatible = "fsl,mpic-msi-v4.
61 reg = <0x41600 0x200 0x44148 4
62 interrupts = <
63 0xe0 0 0 0
64 0xe1 0 0 0
65 0xe2 0 0 0
66 0xe3 0 0 0
67 0xe4 0 0 0
68 0xe5 0 0 0
69 0xe6 0 0 0
70 0xe7 0 0 0
71 0x100 0 0 0
72 0x101 0 0 0
73 0x102 0 0 0
74 0x103 0 0 0
75 0x104 0 0 0
76 0x105 0 0 0
77 0x106 0 0 0
78 0x107 0 0 0>;
79 };
80
81 The Freescale hypervisor and msi-address-64
82 -------------------------------------------
83 Normally, PCI devices have access to all of CC
84 Freescale MSI driver calculates the address of
85 block) and sets that address as the MSI messag
86
87 In a virtualized environment, the hypervisor m
88 mapping for MSIIR. The Freescale ePAPR hyperv
89 because of hardware limitations of the Periphe
90 (PAMU), which is currently the only IOMMU that
91 The ATMU is programmed with the guest physical
92 intercepts transactions and reroutes them to t
93
94 In the PAMU, each PCI controller is given only
95 PAMU restricts DMA operations so that they can
96 Because PCI devices must be able to DMA to mem
97 be used to cover all of the guest's memory spa
98
99 PAMU primary windows can be divided into 256 s
100 subwindow can have its own address mapping ("g
101 physical"). However, each subwindow has to ha
102 means they cannot be located at just any addre
103 restrictions, it is usually impossible to crea
104 covers MSIIR where it's normally located.
105
106 Therefore, the hypervisor has to create a subw
107 primary window used for memory, but mapped to
108 lives). The first subwindow after the end of
109 this. The address specified in the msi-addres
110 address of MSIIR. The hypervisor configures t
111 the true physical address of MSIIR.
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