1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm 4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX TPM PWM controller 7 title: Freescale i.MX TPM PWM controller
8 8
9 maintainers: 9 maintainers:
10 - Shawn Guo <shawnguo@kernel.org> 10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de> 11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com> 12 - Fabio Estevam <festevam@gmail.com>
13 13
14 description: | 14 description: |
15 The TPM counter and period counter are share 15 The TPM counter and period counter are shared between multiple
16 channels, so all channels should use same pe 16 channels, so all channels should use same period setting.
17 17
18 allOf: 18 allOf:
19 - $ref: pwm.yaml# 19 - $ref: pwm.yaml#
20 20
21 properties: 21 properties:
22 "#pwm-cells": 22 "#pwm-cells":
23 const: 3 23 const: 3
24 24
25 compatible: 25 compatible:
26 enum: 26 enum:
27 - fsl,imx7ulp-pwm 27 - fsl,imx7ulp-pwm
28 28
29 reg: 29 reg:
30 maxItems: 1 30 maxItems: 1
31 31
32 assigned-clocks: 32 assigned-clocks:
33 maxItems: 1 33 maxItems: 1
34 34
35 assigned-clock-parents: 35 assigned-clock-parents:
36 maxItems: 1 36 maxItems: 1
37 37
38 clocks: 38 clocks:
39 maxItems: 1 39 maxItems: 1
40 40
41 required: 41 required:
42 - compatible 42 - compatible
43 - reg 43 - reg
44 - clocks 44 - clocks
45 45
46 additionalProperties: false 46 additionalProperties: false
47 47
48 examples: 48 examples:
49 - | 49 - |
50 #include <dt-bindings/clock/imx7ulp-clock. 50 #include <dt-bindings/clock/imx7ulp-clock.h>
51 51
52 pwm@40250000 { 52 pwm@40250000 {
53 compatible = "fsl,imx7ulp-pwm"; 53 compatible = "fsl,imx7ulp-pwm";
54 reg = <0x40250000 0x1000>; 54 reg = <0x40250000 0x1000>;
55 assigned-clocks = <&pcc2 IMX7ULP_CLK_L 55 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
56 assigned-clock-parents = <&scg1 IMX7UL 56 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
57 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; 57 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
58 #pwm-cells = <3>; 58 #pwm-cells = <3>;
59 }; 59 };
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