1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediate
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: MediaTek PWM Controller
8
9 maintainers:
10 - John Crispin <john@phrozen.org>
11
12 allOf:
13 - $ref: pwm.yaml#
14
15 properties:
16 compatible:
17 oneOf:
18 - enum:
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
21 - mediatek,mt7622-pwm
22 - mediatek,mt7623-pwm
23 - mediatek,mt7628-pwm
24 - mediatek,mt7629-pwm
25 - mediatek,mt7981-pwm
26 - mediatek,mt7986-pwm
27 - mediatek,mt7988-pwm
28 - mediatek,mt8183-pwm
29 - mediatek,mt8365-pwm
30 - mediatek,mt8516-pwm
31 - items:
32 - enum:
33 - mediatek,mt8195-pwm
34 - const: mediatek,mt8183-pwm
35
36 reg:
37 maxItems: 1
38
39 "#pwm-cells":
40 const: 2
41
42 interrupts:
43 maxItems: 1
44
45 clocks:
46 minItems: 2
47 maxItems: 10
48
49 clock-names:
50 description:
51 This controller needs two input clocks f
52 clock for each PWM output.
53 minItems: 2
54 items:
55 - const: top
56 - const: main
57 - const: pwm1
58 - const: pwm2
59 - const: pwm3
60 - const: pwm4
61 - const: pwm5
62 - const: pwm6
63 - const: pwm7
64 - const: pwm8
65
66 required:
67 - compatible
68 - reg
69 - clocks
70 - clock-names
71
72 additionalProperties: false
73
74 examples:
75 - |
76 #include <dt-bindings/interrupt-controller
77 #include <dt-bindings/clock/mt2712-clk.h>
78 #include <dt-bindings/interrupt-controller
79
80 pwm0: pwm@11006000 {
81 compatible = "mediatek,mt2712-pwm";
82 reg = <0x11006000 0x1000>;
83 #pwm-cells = <2>;
84 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVE
85 clocks = <&topckgen CLK_TOP_PWM_SEL>,
86 <&pericfg CLK_PERI_PWM0>, <&p
87 <&pericfg CLK_PERI_PWM2>, <&p
88 <&pericfg CLK_PERI_PWM4>, <&p
89 <&pericfg CLK_PERI_PWM6>, <&p
90 clock-names = "top", "main",
91 "pwm1", "pwm2",
92 "pwm3", "pwm4",
93 "pwm5", "pwm6",
94 "pwm7", "pwm8";
95 };
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