1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediate
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: MediaTek DISP_PWM Controller
8
9 maintainers:
10 - Jitao Shi <jitao.shi@mediatek.com>
11
12 allOf:
13 - $ref: pwm.yaml#
14
15 properties:
16 compatible:
17 oneOf:
18 - enum:
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
21 - mediatek,mt8173-disp-pwm
22 - mediatek,mt8183-disp-pwm
23 - items:
24 - enum:
25 - mediatek,mt6795-disp-pwm
26 - mediatek,mt8167-disp-pwm
27 - const: mediatek,mt8173-disp-pwm
28 - items:
29 - enum:
30 - mediatek,mt8186-disp-pwm
31 - mediatek,mt8188-disp-pwm
32 - mediatek,mt8192-disp-pwm
33 - mediatek,mt8195-disp-pwm
34 - mediatek,mt8365-disp-pwm
35 - const: mediatek,mt8183-disp-pwm
36
37 reg:
38 maxItems: 1
39
40 "#pwm-cells":
41 const: 2
42
43 interrupts:
44 maxItems: 1
45
46 clocks:
47 items:
48 - description: Main Clock
49 - description: Mm Clock
50
51 clock-names:
52 items:
53 - const: main
54 - const: mm
55
56 power-domains:
57 maxItems: 1
58
59 required:
60 - compatible
61 - reg
62 - clocks
63 - clock-names
64
65 additionalProperties: false
66
67 examples:
68 - |
69 #include <dt-bindings/interrupt-controller
70 #include <dt-bindings/clock/mt8173-clk.h>
71 #include <dt-bindings/interrupt-controller
72
73 pwm0: pwm@1401e000 {
74 compatible = "mediatek,mt8173-disp-pwm
75 reg = <0x1401e000 0x1000>;
76 #pwm-cells = <2>;
77 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
78 <&mmsys CLK_MM_DISP_PWM0MM>;
79 clock-names = "main", "mm";
80 };
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